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參數(shù)資料
| 型號： | 70V18L15PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 9 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 157K |
| 代理商： | 70V18L15PF8 |
9
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTES:
1. DOR = DOL = VIL,
CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/
W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
Timing Waveform of Semaphore Write Contention(1,3,4)
NOTES:
1.
CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O8) equal to the semaphore value.
SEM
4854 drw 09
tAW
tEW
I/O
VALID ADDRESS
tSAA
R/
W
tWR
tOH
tACE
VALID ADDRESS
DATA
VALID
IN
DATAOUT
tDW
tWP
tDH
tAS
tSWRD
tAOE
Read Cycle
Write Cycle
A0-A2
OE
VALID(2)
tSOP
SEM"A"
4854 drw 10
tSPS
MATCH
R/
W"A"
MATCH
A0"A"-A2"A"
SIDE
"A"
(2)
SEM"B"
R/
W"B"
A0"B"-A2"B"
SIDE
"B"
(2)
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