參數(shù)資料
型號: 70V05S55J8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 8K X 8 DUAL-PORT SRAM, 55 ns, PQCC68
封裝: 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
文件頁數(shù): 4/22頁
文件大?。?/td> 159K
代理商: 70V05S55J8
6.42
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
NOTE:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
SEM"A"
2941 drw 11
tSPS
MATCH
R/
W"A"
MATCH
A0"A"-A2"A"
SIDE
"A"
(2)
SEM"B"
R/
W"B"
A0"B"-A2"B"
SIDE
"B"
(2)
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
SEM
2941 drw 10
tAW
tEW
tSOP
DATA0
VALID ADDRESS
tSAA
R/
W
tWR
tOH
ttACE
VALID ADDRESS
DATAIN VALID
DATA OUT
tDW
tWP
tDH
tAS
tSWRD
tAOE
tSOP
Read Cycle
Write Cycle
A0-A2
OE
VALID(2)
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