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參數(shù)資料
| 型號： | 7015L35GGB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 8K X 9 DUAL-PORT SRAM, 35 ns, CPGA68 |
| 封裝： | 1.18 X 1.18 INCH, 0.16 INCH HEIGHT, GREEN, CERAMIC, PGA-68 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 165K |
| 代理商： | 7015L35GGB |
6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
16
APRIL 04, 2006
Truth Table IV — Address BUSY
Arbitration
NOTES:
1. Pins
BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT7015 are
push-pull, not open drain outputs. On slaves the
BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either
BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
3.
CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT7015 provides two ports with separate control, address and
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
inmemory.TheIDT7015hasanautomaticpowerdownfeaturecontrolled
by
CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (
CE HIGH).
When a port is enabled, access to the entire memory array is permitted.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
or message center) is assigned to each port. The left port interrupt flag
(
INTL) is asserted when the right port writes to memory location 1FFE
where a write is defined as the
CE = R/W = VIL per Truth Table III. The
leftportclearstheinterruptbyanaddresslocation1FFEaccesswhen
CER
=
OER =VIL, R/W is a "don't care". Likewise, the right port interrupt flag
(INTR) is asserted when the left port writes to memory location 1FFF and
tocleartheinterruptflag(
INTR),therightportmustaccess memory location
1FFF. The message (9 bits) at 1FFE or 1FFF isuser-defined since it is
anaddressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations 1FFE and 1FFF are not used as mail boxes but are still part
of the random access memory. Refer to Table III for the interrupt
operation.
Inputs
Outputs
Function
CEL
CER
AOL-A12L
AOR-A12R
BUSYL(1)
BUSYR(1)
X
NO MATCH
H
Normal
H
X
MATCH
H
Normal
X
H
MATCH
H
Normal
L
MATCH
(2)
Write Inhibit(3)
2954 tbl 17
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
2954 tbl 18
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