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參數資料
| 型號： | 7015L35GGB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 8K X 9 DUAL-PORT SRAM, 35 ns, CPGA68 |
| 封裝： | 1.18 X 1.18 INCH, 0.16 INCH HEIGHT, GREEN, CERAMIC, PGA-68 |
| 文件頁數： | 2/20頁 |
| 文件大?。?/td> | 165K |
| 代理商： | 7015L35GGB |
6.42
IDT7015S/L
High-Speed 8K x 9 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
10
APRIL 04, 2006
NOTES:
1. R/
W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW
CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of
CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If
OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If
OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified
tWP.
9. To access RAM,
CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
CE or SEM
(6)
(4)
(3)
2954 drw 09
(7)
(9)
(7)
tLZ
,
tHZ
(7)
2954 drw 10
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
CE or SEM
R/
W
tAW
tEW
(3)
(2)
(6)
(9)
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
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