Advance Information
MC68HC908MR16/MC68HC908MR32
—
Rev. 5.0
372
Electrical Specifications
MOTOROLA
Electrical Specifications
22.6 DC Electrical Characteristics (V
DD
= 5.0 Vdc
±
10%)
Characteristic
Output high voltage
(I
Load
=
–
2.0 mA) all I/O pins
Output low voltage
(I
Load
= 1.6 mA) all I/O pins
PWM pin output source current
(V
OH
= V
DD
–
0.8 V)
PWM pin output sink current (V
OL
= 0.8 V)
Input high voltage, all ports, IRQs, RESET, OSC1
Input low voltage, all ports, IRQs, RESET, OSC1
V
DD
supply current
Run
(3)
Wait
(4)
Stop
(5)
I/O ports high-impedance leakage current
Input current (input only pins)
Capacitance
Ports (as input or output)
Low-voltage inhibit reset
(9)
Low-voltage reset/recover hysteresis
Low-voltage inhibit reset recovery
(V
REC1
= V
LVR1
+ V
LVH1
)
Low-voltage inhibit reset
Low-voltage reset/recover hysteresis
Low-voltage inhibit reset recovery
(V
REC2
= V
LVR2
+ V
LVH2
)
POR re-arm voltage
(6)
POR rise time ramp rate
(8)
POR reset voltage
Monitor mode entry voltage (on IRQ)
Symbol
Min
Typ
(2)
Max
Unit
V
OH
V
DD
–
0.8
—
—
V
V
OL
—
—
0.4
V
I
OH
–
7
—
—
mA
I
OL
V
IH
V
IL
20
—
—
—
—
V
DD
mA
V
V
0.7 x V
DD
V
SS
0.3 x V
DD
I
DD
—
—
—
—
—
—
30
12
700
mA
mA
μ
A
I
IL
I
In
—
—
—
—
4.0
40
—
—
—
—
4.35
90
±
10
±
1
12
8
4.65
150
μ
A
μ
A
C
Out
C
In
V
LVR1
V
LVH1
pF
V
mV
V
REC1
4.04
4.5
4.75
V
V
LVR2
V
LVH2
3.85
150
4.15
210
4.45
250
V
mV
V
REC2
4.0
4.4
4.6
V
V
POR
R
POR
V
PORRST
V
Hi
0
—
—
700
—
100
—
800
mV
V/ms
V
V
0.035
0
V
DD
+ 2.5
V
DD
+ Hi
1. V
DD
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25
°
C only.
3. Run (operating) I
DD
measured using external square wave clock source (f
OSC
= 8.2 MHz). All inputs 0.2 V from rail; no
dc loads; less than 100 pF on all outputs. C
L
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly
affects run I
DD
; measured with all modules enabled
4. Wait I
DD
measured using external square wave clock source (f
OSC
= 8.2 MHz); all inputs 0.2 V from rail; no dc loads;
less than 100 pF on all outputs. C
L
= 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects
wait I
DD
; measured with PLL and LVI enabled
5. Stop I
DD
measured with PLL and LVI disengaged, OCS1 grounded, no port pins sourcing current. It is measured
through combination of V
DD
, V
DDAD
, and V
DDA
.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum V
DD
is not reached before the internal POR is released, RST must be driven low externally until
minimum V
DD
is reached.
9. The low-voltage inhibit reset is software selectable. Refer to
Section 18. Low-Voltage Inhibit (LVI)
.