Pinout and Signal Descriptions
68HC(9)12DG128 Rev 1.0
46
Pinout and Signal Descriptions
MOTOROLA
Setting the RDPT bit in the TMSK2 register configures all port T outputs
to have reduced drive levels. Levels are at normal drive capability after
reset. The TMSK2 register can be read or written anytime after reset
Refer to
Enhanced Capture Timer
.
Table 8 XC68HC912D60 Port Description Summary
Port Name
Pin Numbers
Data Direction
Register
(Address)
In/Out
DDRA ($0002)
Description
112-pin
Port A
PA[7:0]
64-57
Port A and port B pins are used for address and data in
expanded modes. The port data registers are not in the
address map during expanded and peripheral mode
operation. When in the map, port A and port B can be read
or written any time.
DDRA and DDRB are not in the address map in expanded
or peripheral modes.
Port B
PB[7:0]
31–24
In/Out
DDRB ($0003)
Port AD1
PAD1[7:0]
Port AD0
PAD0[7:0]
Port CAN1
PCAN1[1:0]
Port CAN0
PCAN0[1:0]
Port IB
PIB[7:4]
84/82/80/78/
76/74/72/70
83/81/79/77/
75/73/71/69
In
Analog-to-digital converter 1 and general-purpose I/O.
In
Analog-to-digital converter 0 and general-purpose I/O.
102–103
PCAN1[1] Out
PCAN1[0] In
PCAN0[1] Out
PCAN0[0] In
In/Out
DDRIB ($00E7)
PE[1:0] In
PE[7:2] In/Out
DDRE ($0009)
In/Out
DDRK ($00FD)
In/Out
DDRP ($0057)
In/Out
DDRS ($00D7)
PCAN1[1:0] are used with the MSCAN1 module and
cannot be used as general purpose I/O.
PCAN0[1:0] are used with the MSCAN0 module and
cannot be used as general purpose I/O.
General purpose I/O. PIB[7:6] are used with the I-Bus
module when enabled.
104–105
98–101
Port E
PE[7:0]
36–39, 53–56
Mode selection, bus control signals and interrupt service
request signals; or general-purpose I/O.
Port K
PK[7,3:0]
Port P
PP[3:0]
Port S
PS[7:0]
13,
108-111
112,
1–3
Page index emulation signals in expanded or peripheral
mode or general-purpose I/O.
General-purpose I/O. PP[3:0] are used with the
pulse-width modulator when enabled.
Serial communications interfaces 1 and 0 and serial
peripheral interface subsystems; or general-purpose I/O.
General-purpose I/O when not enabled for input capture
and output compare in the timer and pulse accumulator
subsystem.
96–89
Port T
PT[7:0]
18–15, 7–4
In/Out
DDRT ($00AF)
22-pins