參數(shù)資料
型號(hào): 5V80001PGGW3
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): XO, clock
英文描述: OTHER CLOCK GENERATOR, PDSO20
封裝: 4.40 MM, ROHS COMPLIANT, TSSOP-20
文件頁(yè)數(shù): 8/15頁(yè)
文件大?。?/td> 294K
代理商: 5V80001PGGW3
IDT5V80001
MOST CLOCK INTERFACE
SYNTHESIZERS
IDT MOST CLOCK INTERFACE
2
IDT5V80001
REV S 083109
Pin Assignment
Frequency Selection Tables
* FOT_IN must be present in order to generate RCLK and
Retimed (RCLK) MOST_Din.
Pin Descriptions
13
4
12
5
11
8
RCLK
VDD
16
3
S1
1
X2
GND
INPUT_COPY
NC
14
2
7
FOT_OUT
MCLK
15
6
20-pin TSSOP
X1
GND
OEM
MOST_Din
VDD
10
9
BYPASS
LFR
17
18
19
20
FOT_IN
S0
LF
RESET
S1 S0
Operating
Frequency (RCLK)
Mode
Sampling
Frequency
0
45.1584 MHz
MOST 25
44.1 kHz
0
1
49.152 MHz
MOST 25
48 kHz
1
0
90.3168 MHz
MOST 50
44.1 kHz
1
98.304 MHz
MOST 50
48 kHz
OEM
MCLK Output
Source for Retiming Block
0
LOW
RCLK (slave node)
1
Running
MCLK (master node)
OEM
Node
Bypass
FOT_OUT
0
Slave
0
Retimed (RCLK) MOST_Din
*
1FOT_IN
1
Master
0
Retimed (MCLK) MOST_Din
1FOT_IN
Pin
Name
Type
Pin Description
1
X2
Input
Connect to 21.504 MHz crystal.
2
X1
Input
Connect to 21.504 MHz crystal.
3
RESET
Input
Low to reset CDR PLL. Internal pull-up resistor.
4
VDD
Power
Connect to 3.3 V supply.
5
FOT_OUT
Output
Output for fiber optic MOST transceiver. 3.3 V LVTTL levels.
6
GND
Power
Connect to ground.
7
S1
Input
Frequency select input pin. See table above. No internal pull-up or pull-down
resistor.
8
FOT_IN
Input
Input to device from fiber optic MOST transceiver. 3.3 V LVTTL levels, 5 V
tolerant.
9
S0
Input
Frequency select input pin. See table above. No internal pull-up or pull-down
resistor.
相關(guān)PDF資料
PDF描述
5V80001PGGI 98.304 MHz, OTHER CLOCK GENERATOR, PDSO20
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