參數(shù)資料
型號: 5V80001PGGW3
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: XO, clock
英文描述: OTHER CLOCK GENERATOR, PDSO20
封裝: 4.40 MM, ROHS COMPLIANT, TSSOP-20
文件頁數(shù): 1/15頁
文件大小: 294K
代理商: 5V80001PGGW3
DATASHEET
MOST CLOCK INTERFACE
IDT5V80001
IDT MOST CLOCK INTERFACE
1
IDT5V80001
REV S 083109
Description
The IDT5V80001 is a high performance clock interface for
use in MOST (Media Oriented Systems Transport)
enabled systems. It can be used in two modes: generating
a master clock for the ring, or performing clock/data
recovery in a slave node.
Features
Packaged in 20-pin TSSOP
-40 to +85°C temperature range (industrial)
Compliant to AEC Q100
Operating voltage of 3.3 V
5 volt tolerant input for FOT
Low jitter generation
Power-down tri-state mode
Advanced, low-power CMOS process
Block Diagram
Crystal
Oscillator
MCLK
X2
X1
Master
PLL
CDR
PLL
INPUT_COPY
S1
S0
BYPASS
FOT_IN
MOST_Din
FOT_OUT
0
1
0
1
MUX
OEM
RCLK
Retiming
RESET
相關(guān)PDF資料
PDF描述
5V80001PGGI 98.304 MHz, OTHER CLOCK GENERATOR, PDSO20
6-1460821-1 MALE-MALE, RF STRAIGHT ADAPTER, PLUG-PLUG
6-1460821-2 MALE-FEMALE, RF STRAIGHT ADAPTER, PLUG-JACK
6-1460821-3 MALE-FEMALE, RF STRAIGHT ADAPTER, PLUG-JACK
6-1460821-4 FEMALE-FEMALE, RF STRAIGHT ADAPTER, JACK-JACK
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