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參數(shù)資料
| 型號： | 5V80001PGGW3 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, TSSOP-20 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 294K |
| 代理商： | 5V80001PGGW3 |
IDT5V80001
MOST CLOCK INTERFACE
SYNTHESIZERS
IDT MOST CLOCK INTERFACE
14
IDT5V80001
REV S 083109
Revision History
Rev.
Originator
Date
Description of Change
A
J. Gazda
08/29/06
Preliminary datasheet.
B
J. Gazda
09/19/06
Changed block diagram and pinout;
C
J. Gazda
09/25/06
Changed from 16-pin TSSOP to 20-pin TSSOP; added timing diagrams; changed pinout
and block diagrams.
D
J. Gazda
09/27/06
New block diagram; changed pinout; added Propagation Delay, Skew, and Clock Jitter
specs; changed High/Low Input/Output level specs.
E
J. Gazda
11/02/06
Changed temperature rating from -40/+85 to -40/+105 °C; added “Mode” and “Sampling
Frequency” to Frequency Selection Table.
F
J. Gazda
12/14/06
Added “Operation” section; added “External Loop Filter” diagram; added RESET# pin;
various modifications to “External Components” text.
G
J. Gazda
02/15/07
Added Feature bullet of “5 V tolerant input for FOT”; add crystal caps and ground to block
diagram; added “Weak pull-down when OEM=0” statement to MCLK pin description.
H
J. Gazda
03/22/07
Added NDK crystal part number; changed “MCLK” to “RCLK” in the conditions for “Data to
clock jitter” spec.
J
J. Gazda
05/31/07
Removed CP reference on External Loop Filter descriptions; removed one capacitor from
“CDR PLL” in Block Diagram.
K
J. Gazda
06/22/07
Reversed ’1’ and ‘0’ on the MUX in the block diagram; removed the bar from “BYPASS”;
added the text “No pull-up” to pin descriptions 7, 9, 12, and 13; removed “Data to clock
jitter” spec from AC char table.
L
J. Gazda
10/09/07
Removed “Lock” pin.
M
T. Nana
12/17/07
Updates to timing diagrams; added “Timing Requiremnets” table; updates to pin
descriptions; multiple updates to AC/DC char tables; added Figure 7.
N
T. Nana
12/26/07
Updates to Block Diagram and Timing diagrams; added new “Operation” information;
added another OEM table for BYPASS and FOT_OUT; updates to AC/DC char tables and
“Timing Requirementts” table; added “Reset Timing Definition” (Fig. 8) and “BYPASS
Timing Definition” (Fig. 9) diagrams.
P
T. Nana
01/08/08
Updates to DC Electrical Char table; One-Sigma Jitter specs added to “Timing
Requirements” table; updates to Timing Diagrams; added jitter and propagation delay
timing diagrams; added One-Sigma Jitter specs to AC Electrical Char table;
Q
T. Nana
02/06/08
Removed OEM and MUX from Block Diagram; updates to "Operation" text; updated
"Propagation Delay" diagram; added additional “Propagation Delay” spec to AC char
table.
R
11/14/08
Moved from Preliminary to Released.
S
D.L.
08/31/09
Added automotive grade ordering info and marking diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5V80013NLGI | 功能描述:IC CLK GENERATION CHIP 20-TSSOP 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:100 |
| 5V80013NLGI8 | 功能描述:IC CLK GENERATION CHIP 20-TSSOP 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:2,500 |
| 5V80014NLGI | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 MEMS CLOCK GENERATOR RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 5V80014NLGI8 | 制造商:Integrated Device Technology Inc 功能描述:MEMS CLOCK GENERATOR 制造商:Integrated Device Technology Inc 功能描述:16 QFN (GREEN) - Tape and Reel |
| 5V80015NLGI | 功能描述:IC CLK GENERATION CHIP 16QFN 制造商:idt, integrated device technology inc 系列:- 包裝:管件 零件狀態(tài):過期 類型:* PLL:是 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大值:- 分頻器/倍頻器:無/無 電壓 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:16-VQFN 裸露焊盤 供應(yīng)商器件封裝:16-QFN（3x3） 標(biāo)準(zhǔn)包裝:100 |
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