參數(shù)資料
型號(hào): 5V19EE904NLGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
封裝: 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32
文件頁數(shù): 9/29頁
文件大?。?/td> 292K
代理商: 5V19EE904NLGI
IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
17
IDT5V19EE904
REV H 042211
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V19EE904. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Recommended Operation Conditions
Symbol
Description
Min
Max
Unit
VDD
Internal Power Supply Voltage
-0.5
+4.6
V
VI
Input Voltage1
1.Input negative and output voltage ratings may be exceeded if the input and output current ratings are observed.
-0.5
+4.6
V
VO
Output Voltage (not to exceed 4.6 V)1
-0.5
VDD+0.5
V
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
-65
150
°C
Symbol
Parameter
Min
Typ
Max
Unit
VDD
Power supply voltage for VDD pins supporting core and
outputs
3.135
3.3
3.465
V
VDDX
Power supply voltage for crystal oscillator. Use filtered
analog power supply if available.
3.135
3.3
3.465
V
AVDD
Analog power supply voltage. Use filtered analog
power supply if available.
3.135
3.3
3.465
V
VDDOX
3.3V VDDO Range
3.0
3.3
3.6
V
2.5V VDDO Range for 2.5V LVTTL
2.25
2.5
2.75
V
1.8V VDDO Range for 1.8V LVTTL
1.7
1.8
1.9
V
TA
Operating temperature, ambient
-40
+85
°C
CLOAD_OUT Maximum load capacitance (3.3V LVTTL only)
15
pF
Maximum load capacitance (1.8V/2.5V LVTTL only)
8
pF
FIN
External reference crystal
8
50
MHz
External reference clock CLKIN
1
200
tPU
Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
0.05
5
ms
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