參數(shù)資料
型號(hào): 5V19EE904NLGI
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
封裝: 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32
文件頁(yè)數(shù): 5/29頁(yè)
文件大小: 292K
代理商: 5V19EE904NLGI
IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
13
IDT5V19EE904
REV H 042211
Each frame starts with a “Start Condition” and ends with an
“End Condition”. These are both generated by the Master
device.
First Byte Transmitted on I2C Bus
External I2C Interface Condition
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
1
0
1
0
1
0
1
MSB
LSB
R/W
ACK from Slave
R/W
0 – Slave will be written by master
1 – Slave will be read by master
The first byte transmitted by the Master is the Slave Address followed by the R/W bit.
The Slave acknowledges by sending a “1” bit.
7-bit slave address
KEY:
From Master to Slave
From Master to Slave, but can be omitted if followed by the correct sequence
Normally, data transfer is terminated by a STOP condition generated by the Master. However, if the Master still wishes to communicate on the bus, it can
generate a separate START condition, and address another Slave address without first generating a STOP condition.
From Slave to Master
SYMBOLS:
ACK - Acknowledge (SDAT LOW)
NACK – Not Acknowledge (SDAT HIGH)
SR – Repeated Start Condition
S – START Condition
P – STOP Condition
SAddress
R/W
ACK
Command Code
ACK
Register
ACK
Data
ACK
P
7-bits
0
1-bit
8-bits: xxxx xx00
1-bit
8-bits
1-bit
8-bits
1-bit
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