參數(shù)資料
型號： 5V19EE904NLGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： 5V SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC32
封裝： 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-32
文件頁數(shù)： 29/29頁
文件大小： 292K
代理商： 5V19EE904NLGI
IDT5V19EE904
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
CLOCK SYNTHESIZER
IDT EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR
9
IDT5V19EE904
REV H 042211
Profile:
Waveform starts with SS_OFFSET, SS_OFFSET + SDJ,
SS_OFFSET + SDJ+1, etc.
Spread Spectrum Using Sinusoidal Profile
Example
FIN = 25MHz, FOUT = 100MHz, Fssc = 33KHz with center
spread of ±2%. Find the necessary spread spectrum
register settings.
Since the spread is center, the SS_OFFSET can be set to
'0'. Solve for the nominal M value; keep in mind that the
nominal M should be chosen to maximize
the VCO. Start with D = 1, using Eq.6 and Eq.7.
MNOM = 1200MHz / 25MHz = 48
Using Eq.4, we arbitrarily choose N = 22, A = 3. Now that we
have the nominal M value, we can determine TSSC and
NSSC by using Eq.8.
Nssc * Tssc = 25MHz / (33KHz * 4) = 190
However, using Eq. 2 and Eq.3, we find that the closest
value is when TSSC = 14 and NSSC = 6. Keep in mind to
maximize the number of samples used
to enhance the profile of the spread spectrum waveform.
Tssc = 14 + 2 = 16
Nssc = 6 * 2 = 12
Nssc * Tssc = 192
Use Eq.10 to determine the value of the
sigma-delta-encoded samples.
±2% =
(ΣΔ * 100)/(64 * 48)
ΣΔ = 61.4
Either round up or down to the nearest integer value.
Therefore, we end up with 61 or 62 for sigma-delta-encoded
samples. Since the sigma-delta-encoded samples must not
exceed 63 with SS_OFFSET set to '0', 61 or 62 is well within
the limits. It is the discretion of the user to define the shape
of the profile that is better suited for the intended application.
Using Eq. 9 again, the actual spread for the
sigma-delta-encoded samples of 56 and 57 are ±1.99% and
±2.02%, respectively.
Use Eq.10 to determine if the X2 bit needs to be set;
Amplitude = 48 * (1.99 or 2.02) / 100/2 = 0.48 < 1
Therefore, the X2 = '0 '. The dither bit is left to the discretion
of the user.
The example above was of a center spread using spread
spectrum. For down spread, the nominal M value can be set
one integer value lower to 47.
Note that the IDT5V19EE904 should not be programmed
with TSSC > '0', SS_OFFSET = '0', and SD = '0' in order to
prevent an unstable state in the modulator.
The PLL loop bandwidth must be at least 10x the
modulation frequency along with higher damping (larger
ωuz) to prevent the spread spectrum from being filtered and
reduce extraneous noise. Refer to the LOOP FILTER
section for more detail on
ωuz. The A[3:0] must be used for
spread spectrum, even if the total multiplier value is an even
integer.
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參數(shù)描述
5V19EE904NLGI8 功能描述:時鐘發(fā)生器及支持產(chǎn)品 EEPROM PROGRAMMABLE PLL AND VCXO RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56
5V1A-ADAPTER 制造商:Distributed By MCM 功能描述:5V 1A Switching AC Power Supply - Micro USB
5V1A-USB 制造商:Gravitech 功能描述:USB WALL ADAPTER 5V 1A
5V1BC 制造商:SEMTECH_ELEC 制造商全稱:SEMTECH ELECTRONICS LTD. 功能描述:Silicon Epitaxial Planar Zener Diodes
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