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參數(shù)資料
| 型號： | 5962R9684502VXA |
| 元件分類： | SRAM |
| 英文描述： | 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68 |
| 封裝： | PGA-68 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 496K |
| 代理商： | 5962R9684502VXA |
12
AC CHARACTERISTICS BUSY CYCLE 1
(VDD = 5.0V±10%)
Notes:
1. Test conditions assume signal transition time of 5ns or less, timing reference levels of V DD /2, input pulse levels of 0.5V to VDD-0.5V, and output
loading of the specified IOL/IOH and 50-pF load capacitance.
2. Violation of t PS (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy.
3. When violating tPS, the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts.
SYMBOL
PARAMETER
7C138 - 45
7C139 - 45
MIN
MAX
7C138 - 55
7C139 - 55
MIN
MAX
UNIT
t
BLA
BUSY LOW from address match
25
30
ns
tBZA
BUSY HIGH-Z from address mismatch
25
30
ns
tBLC
BUSY LOW from CE LOW
25
30
ns
tBZC
BUSY HIGH from CE HIGH
25
30
ns
tPS
2,3
Port set-up for priority
5
ns
tWB
R/W LOW after BUSY LOW
0
ns
t
WH
R/W HIGH after BUSY HIGH
40
50
ns
tBDD
BUSY HIGH to data valid
45
55
ns
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