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參數(shù)資料
| 型號： | 5962R9684502VXA |
| 元件分類： | SRAM |
| 英文描述： | 4K X 9 DUAL-PORT SRAM, 45 ns, PGA68 |
| 封裝： | PGA-68 |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 496K |
| 代理商： | 5962R9684502VXA |
8
Figure 3b. Read Cycle 2
CE
OE
Data Out
tLZCE
t
LZOE
t
DOE
tACE
tHZOE
t
HZCE
Figure 3c. Read Timing with Port-to-Port Delay
Address
R/W
R
Data
INR
AddressL
DATAOUTL
tWC
MATCH
t
PWE
tSD
tHD
VALID
MATCH
VALID
tDDD
t
WDD
Assumptions:
1. Address valid prior to or coincident with CE transition LOW
2. R/W is HIGH for read cycle
Assumptions:
1. BUSY = HIGH for the writing port
2. CE L = CER = LOW
Address
Data Out
Figure 3a. Read Cycle 1
t
RC
t
OHA
tAA
Data Valid
Assumptions:
1.R/W is HIGH for read cycle
2.Device is continuously selected CE =LOW and OE=LOW
Previous Data Valid
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