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參數(shù)資料
| 型號： | 5962G9215309VMX |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 55 ns, CDIP28 |
| 封裝： | 0.600 X 1.400 INCH, 0.100 INCH PITCH, SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 144K |
| 代理商： | 5962G9215309VMX |
3
WRITE CYCLE
A combination of W less than VIL(max), E1 less than VIL(max),
and E2 greater than VIH(min) defines a write cycle. The state of
G is a “don’t care” for a write cycle. The outputs are placed in
the high-impedance state when either G is greater than
VIH(min), or when W is less than VIL(max).
Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated by W going high, with
E1 and E2 still active. The write pulse width is defined by tWLWH
when the write is initiated by W, and by tETWH when the write
is initiated by the latter of E1 or E2. Unless the outputs have
been previously placed in the high-impedance state by G, the
user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in
figure 4b, is defined by a write terminated by the latter of E1 or
E2 going inactive. The write pulse width is defined by tWLEF
when the write is initiated by W, and by tETEF when the write
is initiated by the latter of E1 or E2 going active. For the W
initiated write, unless the outputs have been previously placed
in the high-impedance state by G, the user must wait tWLQZ
before applying data to the eight bidirectional pins DQ(7:0) to
avoid bus contention.
RADIATION HARDNESS
The UT7156 SRAM incorporates special design and layout
features which allow operation in high-level radiation
environments.
Table 2. Radiation Hardness
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils of
Aluminum.
Total Dose
1.0E6
rads(Si)
Error Rate2
1.0E-10
Errors/Bit-Day
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