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參數(shù)資料
| 型號： | 5962G0151601VXA |
| 元件分類： | PROM |
| 英文描述： | 8K X 8 OTPROM, 55 ns, CDIP28 |
| 封裝： | 0.600 X 1.400 INCH, 2.54 MM PITCH, CERAMIC, DIP-28 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 152K |
| 代理商： | 5962G0151601VXA |
4
READ CYCLE
A combination of PE greater than VIH(min), and CE less than
VIL(max) defines a read cycle. Read access time is measured
from the latter of device enable, output enable, or valid address
to valid data output.
An address access read is initiated by a change in address inputs
while the chip is enabled with OE asserted and PE deasserted.
Valid data appears on data output, DQ(7:0), after the specified
tAVQV is satisfied. Outputs remain active throughout the entire
cycle. As long as device enable and output enable are active, the
address inputs may change at a rate equal to the minimum read
cycle time.
The chip enable-controlled access is initiated byCE going active
while OE remains asserted, PE remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
t
ELQV is satisfied, the eight-bit word addressed by A(12:0)
appears at the data outputs DQ(7:0).
Output enable-controlled access is initiated by OE going active
while CE is asserted, PE is deasserted, and the addresses are
stable. Read access time is tGLQV unless tAVQV or tELQV have
not been satisfied.
AC CHARACTERISTICS READ CYCLE (Post-Radiation)*
(VDD = 3.0V to 3.6V; -55°C < TC < +125°C)
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019 at 1.0E6 rads(Si).
1. Functional test.
2. Three-state is defined as a 400mV change from steady-state output voltage.
SYMBOL
PARAMETER
28F64-55
MIN
MAX
UNIT
t
AVAV
1
Read cycle time
55
ns
tAVQV
Read access time
55
ns
tAXQX
2
Output hold time
0
ns
t
GLQX
2
OE-controlled output enable time
0
ns
tGLQV
OE-controlled access time
25
ns
tGHQZ
OE-controlled output three-state time
25
ns
tELQX
2
CE-controlled output enable time
0
ns
t
ELQV
CE-controlled access time
55
ns
tEHQZ
CE-controlled output three-state time
25
ns
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