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參數(shù)資料
| 型號： | 5962F0520601VZC |
| 元件分類： | ADC |
| 英文描述： | PROPRIETARY METHOD ADC, CQFP128 |
| 封裝： | CERAMIC, QFP-128 |
| 文件頁數(shù)： | 8/42頁 |
| 文件大?。?/td> | 1310K |
| 代理商： | 5962F0520601VZC |
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Specification Definitions
APERTURE (SAMPLING) DELAY
is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode the aperture delay time
(t
AD) after the input clock goes low.
APERTURE JITTER (t
AJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.
Bit Error Rate (B.E.R.)
is the probability of error and is de-
fined as the probable number of errors per unit of time divided
by the number of bits seen in that amount of time. A B.E.R. of
10-18 corresponds to a statistical error in one bit about every
four (4) years.
CLOCK DUTY CYCLE
is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock pe-
riod.
DIFFERENTIAL NON-LINEARITY (DNL)
is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 1 GSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS)
is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD
1.76) / 6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW)
is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR
is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full-
Scale Errors:
Positive Gain Error = Offset Error Positive Full-Scale
Error
Negative Gain Error = (Offset Error Negative Full-
Scale Error)
Gain Error = Negative Full-Scale Error Positive Full-
Scale Error = Positive Gain Error + Negative Gain Error
INTEGRAL NON-LINEARITY (INL)
is a measure of the de-
viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The best fit method is used.
INTERMODULATION DISTORTION (IMD)
is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT)
is the bit that has the small-
est value or weight of all bits. This value is
V
FS / 2
n
where V
FS is the differential full-scale amplitude of 650 mV or
870 mV as set by the FSR input and "n" is the ADC resolution
in bits, which is 8 for the ADC08D1000.
LVDS DIFFERENTIAL OUTPUT VOLTAGE (V
OD) is the ab-
solute value of the difference between the V
D+ & VD- outputs;
each measured with respect to Ground.
20180246
FIGURE 1.
LVDS OUTPUT OFFSET VOLTAGE (V
OS) is the midpoint
between the D+ and D- pins output voltage; ie., [(V
D+) +
( V
D-)]/2.
MISSING CODES
are those output codes that are skipped
and will never appear at the ADC outputs. These codes can-
not be reached with any input value.
MSB (MOST SIGNIFICANT BIT)
is the bit that has the largest
value or weight. Its value is one half of full scale.
NEGATIVE FULL-SCALE ERROR (NFSE)
is a measure of
how far the last code transition is from the ideal 1/2 LSB above
a differential 435 mV with the FSR pin high, or 1/2 LSB above
a differential 325 mV with the FSR pin low. For the AD-
C08D1000 the reference voltage is assumed to be ideal, so
this error is a combination of full-scale error and reference
voltage error.
OFFSET ERROR (V
OFF) is a measure of how far the mid-
scale point is from the ideal zero voltage differential input.
Offset Error = Actual Input causing average of 8k sam-
ples to result in an average code of 127.5.
OUTPUT DELAY (t
OD) is the time delay (in addition to
Pipeline Delay) after the falling edge of DCLK before the data
update is present at the output pins.
OVER-RANGE RECOVERY TIME
is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated ac-
curacy.
PIPELINE DELAY (LATENCY)
is the number of input clock
cycles between initiation of conversion and when that data is
presented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the t
OD.
POSITIVE FULL-SCALE ERROR (PFSE)
is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential +435 mV with the FSR pin high, or 1-1/2
LSB below a differential +325 mV with the FSR pin low. For
the ADC08D1000 the reference voltage is assumed to be
ideal, so this error is a combination of full-scale error and ref-
erence voltage error.
POWER SUPPLY REJECTION RATIO (PSRR)
can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full-scale error that results from a power supply
voltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is a
measure of how well an a.c. signal riding upon the power
supply is rejected from the output and is measured with a 248
MHz, 50 mV
P-P signal riding upon the power supply. It is the
ratio of the output amplitude of that signal at the output to its
amplitude on the power supply pin. PSRR is expressed in dB.
www.national.com
16
ADC08D1000QML
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962F0521201VXC | 制造商:STMicroelectronics 功能描述:16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLO- W/BUS HOLD, 3.3 VOLT. - Bulk |
| 5962F1023501KXA | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
| 5962F1023502K4A | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
| 5962F1023502K5A | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
| 5962F1023502K6A | 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk |
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