參數(shù)資料
型號(hào)： 5962F0520601VZC
元件分類： ADC
英文描述： PROPRIETARY METHOD ADC, CQFP128
封裝： CERAMIC, QFP-128
文件頁(yè)數(shù)： 39/42頁(yè)
文件大小： 1310K
代理商： 5962F0520601VZC
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
100 / 61
101 / 60
102 / 59
103 / 58
DI7 / DQ7
DI7+ / DQ7+
DI6 / DQ6
DI6+ / DQ6+
DI5 / DQ5
DI5+ / DQ5+
DI4 / DQ4
DI4+ / DQ4+
DI3 / DQ3
DI3+ / DQ3+
DI2 / DQ2
DI2+ / DQ2+
DI1 / DQ1
DI1+ / DQ1+
DI0 / DQ0
DI0+ / DQ0+
I and Q channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the DId and DQd outputs,
these outputs represent the later time samples. These outputs
should always be terminated with a 100
differential resistor.
104 / 57
105 / 56
106 / 55
107 / 54
111 / 50
112 / 49
113 / 48
114 / 47
115 / 46
116 / 45
117 / 44
118 / 43
122 / 39
123 / 38
124 / 37
125 / 36
DId7 / DQd7
DId7+ / DQd7+
DId6 / DQd6
DId6+ / DQd6+
DId5 / DQd5
DId5+ / DQd5+
DId4 / DQd4
DId4+ / DQd4+
DId3 / DQd3
DId3+ / DQd3+
DId2 / DQd2
DId2+ / DQd2+
DId1 / DQd1
DId1+ / DQd1+
DId0 / DQd0
DId0+ / DQd0+
I and Q channel LVDS Data Outputs that are delayed by one CLK
cycle in the output demultiplexer. Compared with the DI/DQ
outputs, these outputs represent the earlier time sample. These
outputs should always be terminated with a 100
differential
resistor.
79
80
OR+
OR-
Out Of Range output. A differential high at these pins indicates that
the differential input is out of range (outside the range ±325 mV or
±435 mV as defined by the FSR pin).
82
81
DCLK+
DCLK-
Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal. This signal is at 1/2 the input clock rate in SDR mode and
at 1/4 the input clock rate in the DDR mode. DCLK outputs are not
active during a calibration cycle.
2, 5, 8, 13,
16, 17, 20,
25, 28, 33,
128
V
A
Analog power supply pins. Bypass these pins to ground.
40, 51 ,62,
73, 88, 99,
110, 121
V
DR
Output Driver power supply pins. Bypass these pins to DR GND.
1, 6, 9, 12,
21, 24, 27,
41
GND
Ground return for V
A.
www.national.com
6
ADC08D1000QML
相關(guān)PDF資料
PDF描述
5962-0623101HUC 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE
5962-0623101HUA 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE
5962-0623101HYC 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE
5962-0623101HYA 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE
5962-0623101HXC 1-OUTPUT 100 W DC-DC REG PWR SUPPLY MODULE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
5962F0521201VXC 制造商:STMicroelectronics 功能描述:16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLO- W/BUS HOLD, 3.3 VOLT. - Bulk
5962F1023501KXA 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk
5962F1023502K4A 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk
5962F1023502K5A 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk
5962F1023502K6A 制造商:International Rectifier 功能描述:RAD HARD ULDO - Bulk
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