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參數(shù)資料
| 型號： | 5962-9957701NXD |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封裝： | GREEN, PLASTIC, TSSOP-32 |
| 文件頁數(shù)： | 14/43頁 |
| 文件大?。?/td> | 426K |
| 代理商： | 5962-9957701NXD |
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THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
21
FIFO DESCRIPTION
In order to facilitate an efficient connection to today’s processors, the THS1206 is supplied with a FIFO. This integrated
FIFO enables a problem-free processing of data with today’s processors. The FIFO is provided as a flexible circular buffer.
The circular buffer integrated in the THS1206 can store up to 16 conversion values. Therefore, the amount of interrupts
to be served by a processor can be reduced significantly.
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
Read Pointer
Trigger Pointer
Write Pointer
Data in FIFO
Free
Figure 29. Circular Buffer
The converted data of the THS1206 is automatically written into the FIFO. To control the writing and reading process, a
write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the location which is read next.
The write pointer indicates the location which contains the last written sample. With a selection of multiple analog input
channels, the converted values are written in a predefined sequence to the circular buffer (autoscan mode). In this way,
the channel information for the reading processor is continually maintained.
The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific trigger
level according to Table 13 in order to choose the configuration which best fits the application. The FIFO provides the signal
DATA_AV, which signals the processor to read the amount of data equal to the trigger level selected in Table 13. The signal
DATA_AV becomes active when the trigger condition is satisfied. The trigger condition is satisfied when as many values
as selected for the trigger level are written into the FIFO.
The signal DATA_AV could be connected to an interrupt input of a processor. In every interrupt service routine call, the
processor must read the amount of data equal to the trigger level from the ADC. The first data represents the first channel
according to the autoscan mode, which is shown in Table 10. The channel information is therefore always maintained.
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相關代理商/技術參數(shù) |
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| 5962-9958101QXC | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| 5962-9958301Q2A | 制造商:Texas Instruments 功能描述:DC DC Cntrlr Single-OUT PWM DC to DC Controller 3.6V to 40V Input 20-Pin LCCC Tube |
| 5962-9958301QPA | 制造商:Texas Instruments 功能描述:DC DC Cntrlr Single-OUT PWM DC to DC Controller 3.6V to 40V Input 8-Pin CDIP Tube |
| 5962-9958302Q2A | 制造商:Texas Instruments 功能描述:DC DC Cntrlr Single-OUT PWM DC to DC Controller 3.6V to 40V Input 20-Pin LCCC Tube |
| 5962-9958302QPA | 制造商:Texas Instruments 功能描述:DC DC Cntrlr Single-OUT PWM DC to DC Controller 3.6V to 40V Input 8-Pin CDIP Tube |
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