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參數(shù)資料
| 型號(hào)： | 5962-9466201MJA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 1.8 us SETTLING TIME, 10-BIT DAC, CDIP24 |
| 封裝： | CERAMIC, DIP-24 |
| 文件頁(yè)數(shù)： | 12/14頁(yè) |
| 文件大?。?/td> | 472K |
| 代理商： | 5962-9466201MJA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)
Timing Diagrams (Continued)
TLH11437 – 12
DACs are written to MSB first
DAC1 is written to first then DACs 2 3 and 4
FIGURE 2 Write to All DACs with Update of Outputs (AU e 1) 10 MHz Maximum CLK Rate
TLH11437 – 13
FIGURE 3 Read One DAC DO LSB First DO Changes on Falling Edge of CLK (AU e 1) 5 MHz Maximum CLK Rate
TLH11437 – 14
DAC1 is read first then DACs 2 3 and 4
FIGURE 4 Read All DACs DO LSB First DO Changes on Falling Edge of CLK (AU e 1) 5 MHz Maximum CLK Rate
7
Obsolete
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