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參數(shù)資料
| 型號： | 5962-9169401MCA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 1 CHANNEL, VIDEO AMPLIFIER, CDIP14 |
| 封裝： | CERDIP-14 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 509K |
| 代理商： | 5962-9169401MCA |
Application Information (Continued)
the input signal, signal-to-noise ratio is maximized. The
maximum allowed input amplitude and from system specifi-
cations, using maximum required gain R
f and Rg can be
calculated.
The output stage op amp is a current-feedback type amplifier
optimized for R
f =1k.Rg can then be computed as:
To determine whether the maximum input amplitude will
overdrive the CLC520, compute:
V
dmax =(Rg+3.0) 0.00135
the maximum differential input voltage for linear operation. If
the maximum input amplitude exceeds the above V
dmax limit,
then CLC520 should either be moved to a location in the
signal chain where input amplitudes are reduced, or the
CLC520 gain A
VMAX should be reduced or the values for Rg
and R
f should be increased. The overall system performance
impact is different based on the choice made.
If the input amplitude is reduced, recompute the impact on
signal-to-noise ratio. If A
VMAX is reduced,
Post CLC520 amplifier gain, should be increased, or another
gain stage added to make up for reduced system gain..
To increase R
g and Rf, where Vdmax = (+VIN)(VIN) the
largest expected peak differential input voltage. Compute the
lowest acceptable value for R
g:
R
g >740Vdmax 3
Operating with R
g larger than this value insures linear op-
eration of the input buffers.
R
f may be computed from selected Rg and AVMAX:
R
f should be > =1k for overall best performance, however
R
f < 1k can be implemented if necessary using a loop gain
reducing resistor to ground on the inverting summing node of
the output amplifier (see application note QA-13 for details).
Printed Circuit Layout
A good high frequency PCB layout including ground plane
construction and power supply bypassing close to the pack-
age are critical to achieving full performance. The amplifier is
sensitive
to
stray
capacitance
to
ground
at
the
Inverting-input (pin12); keep node trace area small. Shunt
capacitance across the feedback resistor should not be used
to compensate for this effect.
For best performance at low maximum gains (A
VMAX<10)
R
g+ and Rg connections should be treated in a similar fash-
ion. Capacitance to ground should be minimized by remov-
ing the ground plane from under the resistor of R
g.
Parasitic or load capacitance directly on the output (pin 10)
degrades phase margin leading to frequency response
peaking. A small series resistor before this capacitance,
effectively reduces this effect (see Settling Time vs. Capaci-
tive Load).
Precision buffed resistors (PRP8351 series from Precision
Resistive Products) must be used for R
f for rated perfor-
mance. Precision buffed resistors are suggested for R
g for
low gain settings (A
VMAX <10). Carbon composition resis-
tors and RN55D metal-film resistors may be used with re-
duced performance.
Evaluation PC boards (part no. 730021) for the CLC520 are
available.
Predicting the output noise
Seven noise sources (e
n,in,ii,iio,ino,eno,Ecore) are used to
model the CLC520 noise performance (
n,in, and
i
i model the equivalent input noise terms for the input buffer
while i
io,ino, and eno model the noise terms for the output
buffer. To simplify the model e
n includes the effect of resistor
R
R
bias is assumed noiseless and its noise contribution is
included in i
io.
An additional term E
core mimics the active device noise
contribution from the Gilbert multiplier core. Core noise is
theoretically zero when the multiplier is set to maximum gain
or zero gain (V
g>1.6V or Vg <0.63V respectively at room
temperature) and reaches a maximum of 37nV/
at
A
VMAX/2.
Several points should be made concerning this model. First,
external component noise contributions need to be factored
in when computing total output referred noise. The only
exception is R
g, where its noise contribution is already fac-
tored in. Second, the model ignores flicker noise contribu-
tions. Applications where noise below approximately 100kHz
must be considered should use this model with caution.
Third, this model very accurately predicts output noise volt-
age for the typical application circuit (see above) but accu-
racy will degrade the component values deviate further from
those in the typical application circuit. In general, however,
01275647
FIGURE 4. CLC520 Noise Model
01275648
FIGURE 5. Equivalent Input Noise Voltage (e
n) vs. Rg
CLC520
www.national.com
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