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參數資料
| 型號： | 5962-9169401MCA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 1 CHANNEL, VIDEO AMPLIFIER, CDIP14 |
| 封裝： | CERDIP-14 |
| 文件頁數： | 16/16頁 |
| 文件大?。?/td> | 509K |
| 代理商： | 5962-9169401MCA |
Application Information
Simplified Circuit Description
A simplified schematic for the CLC520 is given in
+V
IN and VIN are buffered with closed-loop voltage follow-
ers inducing a signal current in R
g
proportional to
(+V
IN)(VIN), the differential input voltage. This current con-
trols a current source which supplies two well matched tran-
sistors, Q1 and Q2.
The current flowing through Q2 is converted to the final
output voltage using R
f and output amplifier, U1. By chang-
ing the fraction of the signal current I which flows through Q2
the gain is changed. This is done by changing the voltage
applied differentially to the bases of Q1 and Q2. For ex-
ample, with V
g = 0, Q1 is on and Q2 is off. With zero signal
current of flowing through Q2 into R
f, the CLC520 is set to
minimum gain. Conversely, with V
g = 2V, Q1 is off and all of
the signal current I flows through Q2 to R
f producing maxi-
mum gain. With V
g set to 1.1V, the bases of Q1 and Q2 are
set to approximately the same voltage, causing their collec-
tor currents to equally divide the signal current I, and estab-
lish the gain at one half the maximum gain.
Typical application circuit
Figure 2 illustrates a voltage-controlled gain block offering
broadband performance in a 50
system environment. The
input signal is applied to pin 3 of the CLC520 and terminating
resistor R2. Gain control signals are applied to pin 2. The net
gain control port input impedance is 50
, set by the parallel
combination of R1 and the 750
input impedance of pin 2 of
the CLC520. R
f is set to the standard value, 1k, and Rg
sets the maximum voltage gain to 10V/V. Output impedance
is set by R
o to 50 so with 50 source and load termina-
tions, the gain is approximately 14dB.
Capacitors C1-C6 provide broadband power supply bypass-
ing. C2 and C5 should be tantalum capacitors. All other
capacitors should be high quality ceramic capacitors (CK-05
or equivalent).
Adjusting offset
Offset can be broken into two parts; an input-referred term
and an output-referred term. The input-referred offset shows
up as a variation in output voltage as V
g is changed. This can
be trimmed using the circuit in
Figure 3 by placing a low
frequency square wave (V
IN = 0 to 2V, into Vg with VIN =0V,
the input referred V
os term shows up as a small square wave
riding a DC value. Adjust R
1 to null the Vos square wave term
to zero. After adjusting the input-referred offset, adjust R2
(with V
IN =0, Vg = 0) until VOUT is zero. Finally, for inverting
applications V
IN may be applied to pin 6 and the offset
adjustment to pin 3. This offset trim does not improve output
offset temperature coefficient.
Selecting component values
Most applications of the CLC520 adjust the gain to maximize
the V
OUT signal. When referred back to the input, this means
01275607
FIGURE 1. CLC520 Simplified Schematic
01275608
FIGURE 2. CLC520 Typical Application Circuit
01275628
FIGURE 3. CLC520 Offset Adjustment Circuitry
(other external elements not shown)
CLC520
www.national.com
9
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