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參數(shù)資料
| 型號： | 5962-9169201Q3C |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CQCC28 |
| 封裝： | CERAMIC, LCC-28 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 364K |
| 代理商： | 5962-9169201Q3C |
MAX6953
2-Wire Interfaced, 2.7V to 5.5V, 4-Digit 5 7
Matrix LED Display Driver
______________________________________________________________________________________
13
Global Blink Enable/Disable (E Data Bit D3) Format
The E bit globally enables or disables the blink feature
of the device (Table 10). When blink is globally
enabled, then the digit data in both planes P0 and P1
are used to control the display (Table 11).
When blink is globally disabled, then only the digit data
in plane P0 is used to control the display. The digit data
in plane P1 is ignored.
Global Blink Timing Synchronization (T Data Bit D4)
Format
By setting the T bit in multiple MAX6953s at the same
time (or in quick succession), the blink timing can be
synchronized across all the devices (Table 12). Note
that the display multiplexing sequence is also reset,
which might give rise to a one-time display flicker when
the register is written.
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Blink function is disabled.
P
X
R
T
0
B
X
S
Blink function is enabled.
P
X
R
T
1
B
X
S
Table 10. Global Blink Enable/Disable (E Data Bit D3) Format
SEGMENT’S
BIT SETTING
IN PLANE P1
SEGMENT’S
BIT SETTING
IN PLANE P0
SEGMENT
BEHAVIOR
00
Segment off
01
Segment on only
during the 1st half of
each blink period
10
Segment on only
during the 2nd half of
each blink period
11
Segment on
Table 11. Digit Register Mapping with
Blink Globally Enabled
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Blink timing counters are unaffected.
P
X
R
0
E
B
X
S
Blink timing counters are reset during the I
2C
acknowledge.
PX
R
1
E
B
XS
Table 12. Global Blink Timing Synchronization (T Data Bit D4) Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Digit data for both planes P0 and P1 are unaffected.
P
X
0
T
E
B
X
S
Digit data for both planes P0 and P1 are cleared during
I
2C acknowledge.
PX
1
T
E
B
X
S
Table 13. Global Clear Digit Data (R Data Bit D5) Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
P1 blink phase
0
X
R
T
E
B
X
S
P0 blink phase
1
X
R
T
E
B
X
S
Table 14. Blink Phase Readback (P Data Bit D7) Format
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