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| 型號： | 5962-8967401QX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 18/34頁 |
| 文件大小： | 860K |
| 代理商： | 5962-8967401QX |
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MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
______________________________________________________________________________________
25
Table 9. Shutdown-Mode Write Command
Table 10. Shutdown-Mode-Bits Write Example
DATA
CONTROL BITS
DATA BITS
DIN
11
10
01
0
X
PDD1PDD0PDC1PDC0PDB1
PDB0
PDA1
PDA0
DATA
CONTROL BITS
DATA BITS
DIN
111
0010
X
010
1
0
10
0
X = Don’t care.
Table 11. Settling-Time-Mode Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
0
1
0
X
SPDD SPDC
SPDBSPDA
X = Don’t care.
Shutdown-Mode Bits (PD_0, PD_1)
Use the shutdown-mode bits and control bits to
shut down each DAC independently. The shutdown-
mode bits determine the output state of the selected
channels. The shutdown-control bits put the selected
channels into shutdown mode. To select the shutdown
mode for DACA–DACD, set PD_0 and PD_1 according
to Table 8 (where “_” is replaced with one of the select-
ed channels (A–D)). The three possible states for unity-
gain versions are 1) normal operation, 2) shutdown with
1k output impedance, and 3) shutdown with 100k
output impedance. The three possible states for force-
sense versions are 1) normal operation, 2) shutdown with
1k output impedance, and 3) shutdown with the output
in a high-impedance state. Table 9 shows the com-
mands for writing to the shutdown-mode bits. Table 10
shows an example of writing the shutdown-control bits.
This command shuts down DACA with 1k to ground
and shuts down DACB–DACD with 100k to ground.
Always write the shutdown-mode-bits command first and
then write the shutdown-control-bits command to proper-
ly shut down the selected channels. The shutdown-
control-bits command can be written at any time after the
shutdown-mode-bits command. It does not have to
immediately follow the shutdown-mode-bits command.
Settling-Time-Mode Bits (SPD_)
The settling-time-mode bits select the settling time (FAST
mode or SLOW mode) of the MAX5580–MAX5585.
Set SPD_ = 1 to select FAST mode or set SPD_ = 0 to
select SLOW mode, where “_” is replaced by A, B, C, or
D, depending on the selected channel (Table 11). FAST
mode provides a 3s maximum settling time, and SLOW
mode provides a 6s maximum settling time.
Table 8. Shutdown-Mode Bits
PD_1
PD_0
DESCRIPTION
00
Shutdown with 1k
termination to ground
on DAC_ output.
01
Shutdown with 100k
termination to
ground on DAC_ output for unity-gain
versions. Shutdown with high-impedance
output for force-sense versions.
1
0
Ignored.
11
DAC_ is powered up in its normal
operating mode.
X = Don’t care.
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