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參數(shù)資料
| 型號： | 5962-0720801VXC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP84 |
| 封裝： | CERAMIC, CFP-84 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 681K |
| 代理商： | 5962-0720801VXC |
www.ti.com
APPLICATION INFORMATION
Theory of Operation
Input Configuration
SGLS378 – MARCH 2008
TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3 VPP differential clock, (unless otherwise noted)
SFDR
SNR
vs
DVDD3 ACROSS TEMPERATURE
Figure 11.
Figure 12.
SFDR
SNR
vs
INPUT FREQUENCY AND SAMPLING FREQUENCY
Figure 13.
Figure 14.
The ADS5463 is a 12 bit, 500 MSPS, monolithic-pipeline, analog-to-digital converter. Its bipolar analog core
operates from 5 V and 3.3 V supplies, while the output uses a 3.3 V supply to provide LVDS-compatible outputs.
The conversion process is initiated by the rising edge of the external input clock. The differential input signal is
captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in
a data latency of 3.5 clock cycles, after which the output data is available as a 12 bit parallel word, coded in
offset binary format.
The analog input for the ADS5463 consists of an analog pseudodifferential buffer followed by a bipolar transistor
track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.
The input common mode is set internally through a 500
resistor connected from 2.4 V to each of the inputs.
This results in a differential input impedance of 1 k
.
Copyright 2008, Texas Instruments Incorporated
15
Product Folder Link(s) :ADS5463-SP
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