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參數(shù)資料
| 型號： | 5962-0720801VXC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP84 |
| 封裝： | CERAMIC, CFP-84 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 681K |
| 代理商： | 5962-0720801VXC |
www.ti.com
CLK
ADS5463M
CLK
0.1
F
m
Clock
Source
S0194-02
Digital Outputs
Power Supplies
Layout Information
SGLS378 – MARCH 2008
Figure 19. Differential Clock
For jitter-sensitive applications, the use of a differential clock has advantages (as with any other ADC) at the
system level. The differential clock allows for common-mode noise rejection at the PCB level. With a differential
clock, the signal-to-noise ratio of the ADC is better for high intermediate frequency applications because the
board clock jitter is superior.
A differential clock also allows for the use of bigger clock amplitudes without exceeding the absolute maximum
ratings. In the case of a sinusoidal clock, this results in higher slew rates and reduces the impact of clock noise
on jitter. Figure 19 shows this approach. See Clocking High Speed Data Converters (SLYT075) for more details.
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1 k
resistors. It is
recommended to use ac coupling, but if this scheme is not possible due to, for instance, asynchronous clocking,
the ADS5463 features good tolerance to clock common-mode variation. Additionally, the internal ADC core uses
both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided.
The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal
(DRY), and an overrange indicator (OVR) that equals a logic high when the output reaches the full-scale limits.
The output format is offset binary. It is recommended to use the DRY signal to capture the output data of the
ADS5463. DRY is source-synchronous to the DATA/OVR bits and operates at the same frequency, creating a
half-rate DDR interface that updates data on both the rising and falling edges of DRY. The ADS5463 digital
outputs are LVDS-compatible. Due to the high data rates, care should be taken not to overload the digital outputs
with too much capacitance, which shortens the data-valid timing window. The values given for timing were
obtained with a measured 14 pF parasitic board capacitance to ground on each LVDS line (or 7-pF differential
parasitic capacitance).
The use of low-noise power supplies with adequate decoupling is recommended. Linear supplies are the
preferred choice versus switched ones, which tend to generate more noise components that can be coupled to
the ADS5463. The ADS5463 uses three power supplies. For the analog portion of the design, a 5 V and 3.3 V
AVDD is used, while the digital portion uses a 3.3 V supply (DVDD). All the ground pins are marked as GND,
although analog and digital grounds are not tied together inside the package.
The evaluation board represents a good guideline of how to lay out the board to obtain the maximum
performance from the ADS5463. General design rules, such as the use of multilayer boards, single ground plane
for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces
should be isolated from any external source of interference or noise, including the digital outputs as well as the
clock traces. The clock signal traces also should be isolated from other signals, especially in applications where
low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when
considering the heat dissipation of the device.
18
Copyright 2008, Texas Instruments Incorporated
Product Folder Link(s) :ADS5463-SP
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