參數(shù)資料
型號(hào)： 5962-0720701VXC
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 1-CH 13-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP84
封裝： CERAMIC, QFP-84
文件頁(yè)數(shù)： 8/22頁(yè)
文件大?。?/td> 706K
代理商： 5962-0720701VXC
www.ti.com
18 pF
13 Bit
250 MSPS
AIN
VREF
ADS5444
+ 5 V
THS4509
CM
348
348
100
100
78.9
VIN
From
50
Source
49.9
49.9
78.9
49.9
49.9
0.22
F
0.22
F
0.1
F
0.1
F
0.22
F
Clock Inputs
CLK
ADS5444
CLK
Square Wave or
Sine Wave
0.01
F
0.01
F
ADS5444-SP
SGLS391 – MARCH 2008
Figure 15. Using the THS4509 with the ADS5444
Besides the OPA695, TI offers a wide selection of single-ended operational amplifiers that can be selected
depending on the application. An RF gain block amplifier, such as the TI THS9001, can also be used with an RF
transformer for high input frequency applications. For applications requiring dc-coupling with the signal source, a
differential input/differential output amplifier like the THS4509 (see Figure 15) is a good solution, as it minimizes
board space and reduces the number of components.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5444.
The 50
resistors and 18 pF capacitor between the THS4509 outputs and ADS5444 inputs (along with the input
capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB).
Input termination is accomplished via the 78.9
resistor and 0.22
F capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22
F capacitor and 49.9 resistor are inserted to ground across
the 78.9
resistor and 0.22
F capacitor on the alternate input to balance the circuit.
Gain is a function of the source impedance, termination, and 348
feedback resistor. See the THS4509 data
sheet for further component values to set proper 50
termination for other common gains.
Because the ADS5444 recommended input common-mode voltage is 2.4 V, the THS4509 is operated from a
single power supply input with VS+ = 5 V and VS– = 0 V (ground). This maintains maximum headroom on the
internal transistors of the THS4509.
The ADS5444 clock input can be driven with either a differential clock signal or a single-ended clock input, with
little or no difference in performance between both configurations. In low-input frequency applications, where jitter
may not be a big concern, the use of single-ended clock (see Figure 16) could save some cost and board space
without any trade-off in performance. When driven on this configuration, it is best to connect CLK to ground with
a 0.01
F capacitor, while CLK is ac-coupled with a 0.01 F capacitor to the clock source, as shown in
Figure 16. Single-Ended Clock
16
Copyright 2008, Texas Instruments Incorporated
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