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參數(shù)資料
| 型號(hào)： | 5962-0720701VXC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 13-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CQFP84 |
| 封裝： | CERAMIC, QFP-84 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 706K |
| 代理商： | 5962-0720701VXC |
www.ti.com
TIMING CHARACTERISTICS
ADS5444-SP
SGLS391 – MARCH 2008
Typical values at TC = 25°C, 50% clock duty cycle, sampling rate = 250 MSPS, AVDD = 5 V, DRVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tA
Aperture delay
500
ps
tJ
Clock slope independent aperture uncertainty (jitter)
200
fs RMS
Latency
4
cycles
Clock Input
tCLK
Clock period
4
ns
tCLKH
Clock pulse width high
2
ns
tCLKL
Clock pulse width low
2
ns
Clock to DataReady (DRY)
tDR
Clock rising to DataReady falling
1.1
ns
tC_DR
Clock rising to DataReady rising
Clock duty cycle = 50% (1)
2.7
3.1
3.5
ns
Clock to DATA, OVR(2)
tr
Data rise time (20% to 80%)
0.6
ns
tf
Data fall time(80% to 20%)
0.6
ns
tsu_c
Data valid to clock (setup time)
3.1
ns
th_c
Clock to invalid data (hold time)
0.2
ns
DataReady (DRY)/DATA, OVR(2)
tsu(DR)
Data valid to DRY
1.5
2
ns
th(DR)
DRY to invalid data
0.9
1.3
ns
(1)
tC_DR = tDR + tCLKH for clock duty cycles other than 50%
(2)
Data is updated with clock falling edge or DRY rising edge.
8
Copyright 2008, Texas Instruments Incorporated
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