參數(shù)資料
型號(hào)： 5962-0520601VZX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： ADC
英文描述： PROPRIETARY METHOD ADC, CQFP128
封裝： CERAMIC, QFP-128
文件頁(yè)數(shù)： 24/42頁(yè)
文件大小： 1310K
代理商： 5962-0520601VZX
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
IMPORTANT NOTE:
The Serial Interface should not be used
when calibrating the ADC. Doing so will impair the perfor-
mance of the device until it is re-calibrated correctly. Pro-
gramming the serial registers will also reduce dynamic
performance of the ADC for the duration of the register access
time. Not recommended for use in Radiation Environ-
ments, See Section 2.1.
TABLE 4. Register Addresses
4-Bit Address
Loading Sequence:
A3 loaded after H0, A0 loaded last
A3
A2
A1
A0
Hex
Register Addressed
0
0h
Reserved
0
1
1h
Configuration
0
1
0
2h
"I" Ch Offset
0
1
3h
"I" Ch Full-Scale
Voltage Adjust
0
1
0
4h
Reserved
0
1
0
1
5h
Reserved
0
1
0
6h
Reserved
0
1
7h
Reserved
1
0
8h
Reserved
1
0
1
9h
Reserved
1
0
1
0
Ah
"Q" Ch Offset
1
0
1
Bh
"Q" Ch Full-Scale
Voltage Adjust
1
0
Ch
Reserved
1
0
1
Dh
DES Enable
1
0
Eh
DES Coarse Adjust
1
Fh
DES Fine Adjust
1.4 REGISTER DESCRIPTION
Eight write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Configuration Register
Addr: 1h (0001b)
W only (0xB2FF)
D15
D14
D13
D12
D11
D10
D9
D8
1
0
1
DCS
DCP
nDE
OV
OE
D7
D6
D5
D4
D3
D2
D1
D0
1
Bit 15
Must be set to 1b
Bit 14
Must be set to 0b
Bit 13
Must be set to 1b
Bit 12
DCS:Duty Cycle Stabilizer. When this bit is set
to 1b , a duty cycle stabilzation circuit is
applied to the clock input. When this bit is set
to 0b the stabilzation circuit is disabled.
POR State: 1b
Bit 11
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
POR State: 0b
Bit 10
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Dual Data
Rate) mode whereby a data word is output
with each rising and falling edge of DCLK.
When this bit is set to a 1b, data bus clocking
follows the SDR (single data rate) mode
whereby each data word is output with either
the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
Bit 9
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mV
P-P is used. When this bit is set to 0b, the
reduced output amplitude of 510 mV
P-P is
used.
POR State: 1b
Bit 8
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as the
OutEdge pin in the normal control mode.
When this bit is 1, the data outputs change with
the rising edge of DCLK+. When this bit is 0,
the data output change with the falling edge of
DCLK+.
POR State: 0b
Bits 7:0
Must be set to 1b.
I-Channel Offset
Addr: 2h (0010b)
W only (0x007F)
D15
D14
D13
D12
D11
D10
D9
D8
(MSB)
Offset Value
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
Sign
1
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