參數(shù)資料
型號(hào)： 5962-0520601VZX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： ADC
英文描述： PROPRIETARY METHOD ADC, CQFP128
封裝： CERAMIC, QFP-128
文件頁(yè)數(shù)： 20/42頁(yè)
文件大小： 1310K
代理商： 5962-0520601VZX
ed. It is important that the input signals are either a.c. coupled
to the inputs with the V
CMO pin grounded, or d.c. coupled with
the V
CMO pin left floating. An input common mode voltage
equal to the V
CMO output must be provided when d.c. coupling
is used.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of
870 mV
P-P, while grounding pin 14 causes an input full-scale
range setting of 650 mV
P-P. The full-scale range setting op-
erates equally on both ADCs.
In the Extended Control mode, the full-scale input range can
be set to values between 560 mV
P-P and 840 mVP-P through
a serial interface. See Section 2.2
1.1.5 Clocking
The ADC08D1000 must be driven with an a.c. coupled, dif-
ferential clock signal. Section 2.4 describes the use of the
clock input pins. A differential LVDS output clock is available
for use in latching the ADC output data into whatever device
is used to receive the data.
The ADC08D1000 offers options for input and output clock-
ing. These options include a choice of Dual Edge Sampling
(DES) or "interleaved mode" where the ADC08D1000 per-
forms as a single device converting at twice the input clock
rate, a choice of which DCLK (DCLK) edge the output data
transitions on, and a choice of Single Data Rate (SDR) or
Double Data Rate (DDR) outputs.
The ADC08D1000 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking especially in the Dual-Edge Sampling mode (DES).
This circuitry allows the ADC to be clocked with a signal
source having a duty cycle ratio of 80 / 20 % (worst case)
for both the normal and the Dual Edge Sampling modes.
1.1.5.1 Dual-Edge Sampling
The DES mode allows one of the ADC08D1000's inputs (I or
Q Channel) to be sampled by both ADCs. One ADC samples
the input on the positive edge of the input clock and the other
ADC samples the same input on the other edge of the input
clock. A single input is thus sampled twice per input clock cy-
cle, resulting in an overall sample rate of twice the input clock
frequency, or 2 GSPS with a 1 GHz input clock.
In this mode the outputs are interleaved such that the data is
effectively demultiplexed 1:4. Since the sample rate is dou-
bled, each of the 4 output buses have a 500 MSPS output rate
with a 1 GHz input clock. All data is available in parallel. The
four bytes of parallel data that are output with each clock is in
the following sampling order, from the earliest to the latest:
DQd, DId, DQ, DI. Table 1 indicates what the outputs repre-
sent for the various sampling possibilities.
In the non-extended mode of operation only the "I" input can
be sampled in the DES mode. In the extended mode of op-
eration the user can select which input is sampled.
The ADC08D1000 also includes an automatic clock phase
background calibration feature which can be used in DES
mode to automatically and continuously adjust the clock
phase of the I and Q channel. This feature removes the need
to adjust the clock phase setting manually and provides opti-
mal Dual-Edge Sampling ENOB performance.
IMPORTANT NOTE:
The background calibration feature in
DES mode does not replace the requirement for On-Com-
mand Calibration which should be run before entering DES
mode, or if a large swing in ambient temperature is experi-
enced by the device.
DES Mode should not be used in radiation environments.
See section 2.1
TABLE 1. Input Channel Samples Produced at Data Outputs
Data Outputs (Always
sourced with respect to fall
of DCLK)
Normal Sampling Mode
Dual-Edge Sampling Mode (DES)
I-Channel Selected
Q-Channel Selected *
DI
"I" Input Sampled with Fall of
CLK 13 cycles earlier.
"I" Input Sampled with Fall of
CLK 13 cycles earlier.
"Q" Input Sampled with Fall of
CLK 13 cycles earlier.
DId
"I" Input Sampled with Fall of
CLK 14 cycles earlier.
"I" Input Sampled with Fall of
CLK 14 cycles earlier.
"Q" Input Sampled with Fall of
CLK 14 cycles earlier.
DQ
"Q" Input Sampled with Fall of
CLK 13 cycles earlier.
"I" Input Sampled with Rise of
CLK 13.5 cycles earlier.
"Q" Input Sampled with Rise
of CLK 13.5 cycles earlier.
DQd
"Q" Input Sampled with Fall of
CLK 14 cycles after being
sampled.
"I" Input Sampled with Rise of
CLK 14.5 cycles earlier.
"Q" Input Sampled with Rise
of CLK 14.5 cycles earlier.
* Note that, in the DES mode, the "Q" channel input can only be selected for sampling in the Extended Control Mode.
27
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ADC08D1000QML
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