參數(shù)資料
型號(hào)： 5962-0520601VZX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： PROPRIETARY METHOD ADC, CQFP128
封裝： CERAMIC, QFP-128
文件頁數(shù)： 22/42頁
文件大?。?/td> 1310K
代理商： 5962-0520601VZX
TABLE 2. Features and modes
Feature
Normal Control Mode
Extended Control Mode
SDR or DDR Clocking
Selected with pin 4
Selected with DE bit in the Configuration
Register
DDR Clock Phase
Not Selectable (0° Phase Only)
Selected with DCP bit in the
Configuration Register. See 1.4
SDR Data transitions with rising or falling
DCLK edge
Selected with pin 4
Selected with the OE bit in the
Configuration Register
LVDS output level
Selected with pin 3
Selected with the OV bit (9)in the
Configuration Register
Power-On Calibration Delay
Delay Selected with pin 127
Short delay only.
Full-Scale Range
Options (650 mV
P-P or 870 mVP-P)
selected with pin 14. Selected range
applies to both channels.
Up to 512 step adjustments over a
nominal range of 560 mV to 840 mV.
Separate range selected for I- and Q-
Channels. Selected using registers 3H
and Bh
Input Offset Adjust
Not possible
Separate ±45 mV adjustments in 512
steps for each channel using registers 2h
and Ah
Dual Edge Sampling Selection
Enabled with pin 127
Enabled through DES Enable Register
Dual Edge Sampling Input Channel
Selection
Only I-Channel Input can be used
Either I- or Q-Channel input may be
sampled by both ADCs
DES Sampling Clock Adjustment
The Clock Phase is adjusted
automatically
Automatic Clock Phase control can be
selected by setting bit 14 in the DES
Enable register (Dh). The clock phase
can also be adjusted manually through
the Coarse & Fine registers (Eh and Fh)
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 3.
TABLE 3. Extended Control Mode Operation (Pin 14 Floating)
Feature
Extended Control Mode Default State
SDR or DDR Clocking
DDR Clocking
DDR Clock Phase
Data changes with DCLK edge (0° phase)
LVDS Output Amplitude
Normal amplitude
(710 mV
P-P)
Calibration Delay
Short Delay
Full-Scale Range
700 mV nominal for both channels
Input Offset Adjust
No adjustment for either channel
Dual Edge Sampling (DES)
Not enabled
1.3 THE SERIAL INTERFACE
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Eight write only registers are acces-
sible through this serial interface.
SCS:
This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK
: Serial data input is accepted with the rising edge of
this signal.
SDATA:
Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 4.
Refer to the Register Description (Section 1.4) for information
on the data to be written to the registers.
29
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ADC08D1000QML
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