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參數(shù)資料
| 型號： | 5241 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and 2-wire Interface |
| 中文描述： | 四數(shù)字可編程電位計（民進黨⑩）與64個龍頭和2線接口 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 111K |
| 代理商： | 5241 |
8
CAT5241
Document No. 2011, Rev. J
INSTRUCTION AND REGISTER
DESCRIPTION
SLAVE ADDRESS BYTE
The first byte sent to the CAT5241 from the master/
processor is called the Slave/DPP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the CAT5241 are
fixed at 0101[B] (refer to Table 1).
The next four bits, A3 - A0, are the internal slave address
and must match the physical device address which is
defined by the state of the A3 - A0 input pins for the
CAT5241 to successfully continue the command
sequence. Only the device which slave address matches
the incoming device address sent by the master executes
the instruction. The A3 - A0 inputs can be actively driven
by CMOS input signals or tied to V
CC
or V
SS
.
INSTRUCTION BYTE
The next byte sent to the CAT5241 contains the instruction
and register pointer information. The four most significant
bits used provide the instruction opcode I [3:0]. The P1
and P0 bits point to one of four Wiper Control Registers.
The least two significant bits, R1 and R0, point to one of
the four data registers of each associated potentiometer.
The format is shown in Table 2.
Table 1. Identification Byte Format
ID3
0
(MSB)
ID2
1
ID1
0
ID0
1
A3
A2
A1
A0
(LSB)
Device Type
Identifier
Slave Address
Table 2. Instruction Byte Format
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
Data Register Selected
R1
R0
DR0
0
0
DR1
0
1
DR2
1
0
DR3
1
1
Data Register Selection
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