參數(shù)資料
型號(hào)： 5241
元件分類： 數(shù)字電位計(jì)
英文描述： Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and 2-wire Interface
中文描述： 四數(shù)字可編程電位計(jì)（民進(jìn)黨⑩）與64個(gè)龍頭和2線接口
文件頁(yè)數(shù)： 5/16頁(yè)
文件大?。?/td> 111K
代理商： 5241
5
CAT5241
Document No. 2011, Rev. J
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
Figure 1. Bus Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
Figure 2. Write Cycle Timing
START BIT
SDA
STOP BIT
SCL
Figure 3. Start/Stop Timing
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
t
WR
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle,
the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
N
END(1)
Endurance
Reference Test Method
Min
Typ
Max
Units
MIL-STD-883, Test Method 1033
1,000,000
Cycles/Byte
T
DR(1)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
V
ZAP(1)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
I
LTH(1)(2)
Latch-Up
JEDEC Standard 17
100
mA
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