參數(shù)資料
型號: 4250
英文描述: Low-Cost, 2.7V to 5.5V Temperature Switches in a SOT23
中文描述: 4250組數(shù)據(jù)表數(shù)據(jù)表652K/NOV.30.97
文件頁數(shù): 51/59頁
文件大?。?/td> 652K
代理商: 4250
50
MITSUBISHI MICROCOMPUTERS
4250 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Set a value to the bit 2 of register K0, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least
one instruction. According to the input state of G
0
/INT pin, the external interrupt request flag (EXF0) may be set to “1” when
the interrupt valid waveform is changed.
CONTROL REGISTERS
PU0
1
PU0
0
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Ports C and K
pull-up transistor control bit
Ports G
0
–G
3
pull-up transistor control bit
Pull-up control register PU0
at reset : 00
2
at RAM back-up : state retained
0
1
0
1
W
V1
3
V1
2
V1
1
V1
0
Port G
1
(I/O)
T
OUT
pin (output) / port G
1
(input)
Prescaler stop (initial state) / timer 1 stop (state retained)
Prescaler/timer 1 operation
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
0
1
0
1
0
1
0
1
G
1
/T
OUT
pin function selection bit
Prescaler/timer 1 operation start bit
Timer 1 interrupt enable bit
External interrupt enable bit
Timer control register V1
R/W
at reset : 0000
2
at RAM back-up : 0000
2
K0
3
K0
2
K0
1
K0
0
Instruction clock divided by 4
Instruction clock divided by 512
Rising waveform (“L”
“H”)
Falling waveform (“H”
“L”)
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
Key-on wakeup not used
Key-on wakeup used (“L” level recognized)
Prescaler dividing ratio selection bit
Interrupt valid waveform for INT pin/
key-on wakeup valid waveform selection
bit (Note 2)
Ports G
1
–G
3
key-on wakeup control bit
Ports S
0
–S
3
key-on wakeup control bit
Key-on wakeup control register K0
at reset : 0000
2
at RAM back-up : state retained
0
1
0
1
0
1
0
1
R/W
Functions
XOR operation
OR operation
AND operation
Not available
Logic operation function selection bits
Logic operation selection register LO
at reset : 00
2
at RAM back-up : 00
2
LO
1
0
0
1
1
W
LO
0
0
1
0
1
LO
1
LO
0
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