
UTC 4052 CMOS
UTC
UNISONIC TECHNOLOGIES CO., LTD.
8
QW-R502-013,A
700
0
300
500
600
-10
Vin,INPUT VOLTAGE (VOLTS)
R
O
,
-8.0
0
0.2
6.0
4.0
400
100
200
-6.0
-4.0
-2.0
10
8.0
Figure12.V
DD
=2.5V,V
EE
=-2.5V
TA=125
℃
25
℃
-55
℃
350
0
-10
150
250
300
Vin, INPUT VOLTAGE (VOLTS)
-8.0
0
0.2
6.0
4.0
200
50
100
-6.0
-4.0
-2.0
10
8.0
Figure13 Comparison at 25
℃
,V
DD
=-VEE
TA=25
℃
R
O
,
V
DD
=2.5V
5.0V
7.5V
Figure A illustrates use of the on–chip level converter detailed in Figures 2. The 0 ~ 5 V Digital Control
signal is used to directly control a 9 Vp–p analog signal.
The digital control logic levels are determined by V
DD
and V
SS
. The V
DD
voltage is the logic high voltage; the V
SS
voltage is logic low. For the example, V
DD
= + 5 V = logic high at the control inputs; V
SS
= GND = 0 V = logic low.
The maximum analog signal level is determined by V
DD
and V
EE
. The V
DD
voltage determines the maximum
recommended peak above V
SS
. The V
EE
voltage determines the maximum swing below V
SS
. For the example, V
DD
–
V
SS
= 5 V maximum swing above V
SS
; V
SS
– V
EE
= 5 V maximum swing below V
SS
. The example shows a ± 4.5 V
signal which allows a 1/2 volt margin at each peak. If voltage transients above V
DD
and/or below V
EE
are anticipated
on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small
signal types able to absorb the maximum anticipated current surges during clipping.
The
absolute
maximum potential difference between V
DD
and V
EE
is 18.0 V. Most parameters are specified up to
15 V which is the
recommended
maximum difference between V
DD
and V
EE
.
Balanced supplies are not required. However, V
SS
must be greater than or equal to V
EE
. For example, V
DD
= + 10
V, V
SS
= + 5 V, and V
EE
– 3 V is acceptable. See the Table below.
+5V
EXTERNAL
CMOS
DIGITAL
CIRCUITRY
0 ~ 5V DIGITAL
CONTROL SIGNALS
ANALOG SIGNAL
9 Vp-p
SWITCH
I/O
INHIBIT,
A,B,C
COMMON
O/I
V
DD
Vss
V
EE
-5V
ANALOG SIGNAL
9 Vp-p
-4.5V
+4.5V
GND
+5V
Figure A. Application Example
4052