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參數(shù)資料
| 型號： | 4052 |
| 廠商： | 友順科技股份有限公司 |
| 英文描述： | ANALOG MULTIPLEXERS /DEMULTIPLEXERS |
| 中文描述： | 模擬多路復(fù)用器/解復(fù)用器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 172K |
| 代理商： | 4052 |
UTC 4052 CMOS
ELECTRICAL CHARACTERISTICS
*5
(C
L
= 50 pF, T
A
= 25
℃
) (V
EE
≤
V
SS
unless otherwise indicated)
PARAMETER
SYMBOL
TEST CONDITIONS
Propagation Delay
Times(Figure 4)
Switch Input to Switch
Output
V
DD
-V
EE=
15, t
PLH
,t
PHL
=(0.06 ns/pF) C
L
+7.0 ns
Propagation Delay
Times(Figure 4)
Inhibit to Output
V
DD
-V
EE=
5.0
V
DD
-V
EE=
10
V
DD
-V
EE=
15
Propagation Delay
Times(Figure 4)
Control Input to Output
V
DD
-V
EE=
10
V
DD
-V
EE=
15
Second Harmonic
Distortion
Bandwidth (Figure 5)
BW
R
L
=1k
Ω
, V
in
=1/2(V
DD
-V
EE
)p-p, C
L
=50pF,
20 Log (V
out
/V
in
)=-3dB,
V
DD
-V
EE=
10
Off Channel
Feedthrough Attenuation
(Figure 5)
Channel Separation
(Figure 6)
V
DD
-V
EE=
10
Crosstalk ,Control Input
to Common O/I (Figure
7)
*5. The formulas given are for the typical characteristics only at 25
℃
.
*6. Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential
*
performance.
UTC
UNISONIC TECHNOLOGIES CO., LTD.
4
QW-R502-013,A
MIN
TYP
*6
MAX UNIT
75
30
25
600
310
250
650
260
180
0.07
t
PLH
,t
PHL
R
L
=10k
Ω
V
DD
-V
EE=
5.0, t
PLH
,t
PHL
=(0.17 ns/pF) C
L
+21.5 ns
V
DD
-V
EE=
10, t
PLH
,t
PHL
=(0.08 ns/pF) C
L
+8.0 ns
30
12
10
300
155
125
325
130
90
ns
t
PHZ
,t
PLZ
t
PZH
,t
PZL
RL=10k
Ω
,VEE=Vss
Output”1” or “0” to High Impedance, or
High Impedance to”1” or “0” Level
ns
t
PLN
,t
PHL
RL=10k
Ω
,V
EE
=Vss
V
DD
-V
EE=
5.0
ns
R
L
=10k
Ω
, f=1kHz, V
in
=5Vpp,
V
DD
-V
EE=
10
%
17
MHz
R
L
=1k
Ω
, Vin=1/2(V
DD
-V
EE
)p-p, Fin=30MHz,
V
DD
-V
EE=
10
-50
dB
RL=1k
Ω
, Vin=1/2(V
DD
-V
EE
)p-p, fin=3.0MHz
,
-50
dB
R1=1k
Ω
, R
L
=10k
Ω
,
Control t
TLH
=t
THL
=20ns ,Inhibit=Vss),
V
DD
-V
EE=
10
75
mV
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| 4052 BROWN | 制造商:Thomas & Betts 功能描述:3-1/4-4",RND CVR,NM,FLAT&BLANK,BROW |
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