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參數(shù)資料
| 型號(hào)： | 4053BC |
| 英文描述： | (189.54 k) |
| 中文描述： | （189.54十一） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 189K |
| 代理商： | 4053BC |
TL/F/5662
C
A
October 1989
CD4051BM/CD4051BC Single 8-Channel Analog
Multiplexer/Demultiplexer
CD4052BM/CD4052BC Dual 4-Channel Analog
Multiplexer/Demultiplexer
CD4053BM/CD4053BC Triple 2-Channel Analog
Multiplexer/Demultiplexer
General Description
These analog multiplexers/demultiplexers are digitally con-
trolled analog switches having low ‘‘ON’’ impedance and
very low ‘‘OFF’’ leakage currents. Control of analog signals
up to 15V
p-p
can be achieved by digital signal amplitudes of
3–15V. For example, if V
DD
e
5V, V
SS
e
0V and V
EE
eb
5V,
analog signals from
b
5V to
a
5V can be controlled by digi-
tal inputs of 0–5V. The multiplexer circuits dissipate ex-
tremely low quiescent power over the full V
DD
b
V
SS
and
V
DD
b
V
EE
supply voltage ranges, independent of the logic
state of the control signals. When a logical ‘‘1’’ is present at
the inhibit input terminal all channels are ‘‘OFF’’.
CD4051BM/CD4051BC is a single 8-channel multiplexer
having three binary control inputs. A, B, and C, and an inhibit
input. The three binary signals select 1 of 8 channels to be
turned ‘‘ON’’ and connect the input to the output.
CD4052BM/CD4052BC is a differential 4-channel multiplex-
er having two binary control inputs, A and B, and an inhibit
input. The two binary input signals select 1 or 4 pairs of
channels to be turned on and connect the differential ana-
log inputs to the differential outputs.
CD4053BM/CD4053BC is a triple 2-channel multiplexer
having three separate digital control inputs, A, B, and C, and
an inhibit input. Each control input selects one of a pair of
channels which are connected in a single-pole double-throw
configuration.
Features
Y
Wide range of digital and analog signal levels: digital
3–15V, analog to 15V
p-p
Y
Low ‘‘ON’’ resistance: 80
X
(typ.) over entire 15V
p-p
sig-
nal-input range for V
DD
b
V
EE
e
15V
Y
High ‘‘OFF’’ resistance: channel leakage of
g
10 pA
(typ.) at V
DD
b
V
EE
e
10V
Y
Logic level conversion for digital addressing signals of
3–15V (V
DD
b
V
SS
e
3–15V) to switch analog signals to
15 V
p-p
(V
DD
b
V
EE
e
15V)
Y
Matched switch characteristics:
D
R
ON
e
5
X
(typ.) for
V
DD
b
V
EE
e
15V
Y
Very low quiescent power dissipation under all digital-
control input and supply conditions: 1
m
W (typ.) at
V
DD
b
V
SS
e
V
DD
b
V
EE
e
10V
Y
Binary address decoding on chip
Connection Diagrams
Dual-In-Line Packages
CD4051BM/CD4051BC
CD4052BM/CD4052BC
CD4053BM/CD4053BC
TL/F/5662–1
Order Number CD4051B, CD4052B, or CD4053B
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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