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參數(shù)資料
| 型號： | 4040FI5 |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit |
| 中文描述： | 4040架F15（3x7683）前端的數(shù)據(jù)資料|射頻調(diào)諧器模塊： |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 725K |
| 代理商： | 4040FI5 |
4040 FI5 RF F
RONT
E
ND
M
ODULE
(3
X
7683, 3
X
7748)
A
DVANCE
D
ATA
S
HEET
M
IXED
D
IGITAL AND
A
NALOG
TV
AND
ATSC A
PPLICATIONS
3X 7683 ED Revision: 07
May 00
Page 8 of 17
7683ED07.doc
P
10
I2C BUS
10.1
WRITE DATA FORMAT FOR I2C BUS
Table 7
Write Data Format
MSB
LSB
ACK
Address byte
1
1
0
0
0
MA1
MA0
R/W
1
A
2
Divider byte 1
0
n14
n13
n12
n11
n10
n9
n8
A
Divider byte 2
n7
n6
n5
n4
n3
n2
n1
n0
A
Control byte 1
1
CP
3
T2
T1
T0
RSA
RSB
OS
A
Control byte 2
P7
P6
P5
P4
P3
P2
P1
P0
A
1
R/W = 0: write mode
2
A = Acknowledge
3
CP = 0:
charge pump current low
10.2
ADDRESS SELECTION FOR I2C BUS
Table 8
Address Selection
MA1
MA0
A
DDRESS
V
OLTAGE AT
P
IN
14
0
0
C0
(0 to 0.1) VS1
0
1
C2
(0.2 to 0.3) VS1 or open circuit
1
0
C4
(0.4 to 0.6) VS1
1
1
C6
(0.9 to 1) VS1
10.3
OSCILLATOR FREQUENCY AND DIVIDER BYTE CALCULATION
Table 9
Oscillator Frequency and Divider Byte Calculation
RSA
RSB
R
EFERENCE
D
IVIDER
M
IN
. T
UNING
S
TEP
F
REF
1
1
512
62.5 kHz
7.8125 kHz
X
0
640
50.0 kHz
6.25 kHz
0
1
1024
31.25 kHz
3.90625 kHz
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