參數(shù)資料
型號(hào): 403GCX-3JC80C2A
元件分類: 復(fù)位半導(dǎo)體
英文描述: 300mA LDO Linear Regulators with Internal Microprocessor Reset Circuit
中文描述: 32位微處理器
文件頁(yè)數(shù): 23/48頁(yè)
文件大?。?/td> 768K
代理商: 403GCX-3JC80C2A
IBM PowerPC 403GC
23
SysClk Timing
Notes:
1. These values do not include the allowable tolerance for clock edge instability represented by T
CS
.
2. Cycle-to-cycle jitter allowed between any two edges.
3. Rise and fall times measured between 0.8V and 2.0V.
Timer Clock and Serial Port Timing Characteristics
Table 13. 403GC Timer Clock and Serial Clock Timings
Notes:
1. Maximum input frequency of TimerClk and SerClk must be less than or equal to half of SysClk input frequency.
2. TimerClk and SerClk input high times must be greater than or equal to SysClk period T
C
.
3. TimerClk and SerClk input low times must also be greater than or equal to SysClk period T
C
.
Table 12. 403GC System Clock Timing
Symbol
Parameter
25 MHz
33 MHz
40 MHz
Units
Min
Max
Min
Max
Min
Max
F
C
SysClk clock input frequency
1
25
33
40
MHz
T
C
SysClk clock period
1
40
30
25
ns
T
CS
Clock edge stability
2
0.2
0.2
0.2
ns
T
CH
Clock input high time
16
13
11
ns
T
CL
Clock input low time
16
13
11
ns
T
CR
Clock input rise time
3
Clock input fall time
3
0.5
2.5
0.5
2.5
0.5
1.5
ns
T
CF
0.5
2.5
0.5
2.5
0.5
1.5
ns
Symbol
Parameter
Min
Max
Units
F
SC
T
SC
T
SCH
T
SCL
TimerClk, SerClk input frequency
0.5 F
C
MHz
TimerClk, SerClk period
2T
C
1/F
C
1/F
C
ns
TimerClk, SerClk input high time
ns
TimerClk, SerClk input low time
ns
T
CR
T
CF
T
CL
T
CH
T
C
2.0V
1.5V
0.8V
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