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參數(shù)資料
| 型號： | 3820 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 37/66頁 |
| 文件大?。?/td> | 1093K |
| 代理商： | 3820 |
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37
MITSUBISHI MICROCOMPUTERS
3820 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away).
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H.
Initial Value of Watchdog Timer
At reset or when writing data into the watchdog timer control reg-
ister, the watchdog timer H is set to “3F
16
” and the watchdog timer
L is set to “FF
16
”. As a write instruction, it is possible to use any in-
struction that can cause a write signal such as STA, LDM and
CLB. Write data except bit 7 has no significance and the above
value is set independently.
Watchdog Timer Operation
The watchdog timer stops at reset and starts a countdown by writ-
ing to the watchdog timer control register. When the watchdog
timer H underflows, an internal reset occurs, and the reset status
is released after waiting the reset release time.
Then the program executes from the reset vector address.
Usually, a program is designed so that data can be written into the
watchdog timer control register before the watchdog timer H
underflows. If data is not written once into the watchdog timer con-
trol register, the watchdog timer does not function.
At execution of the STP instruction, both clock and watchdog timer
stops. At the same time that the stop mode is released, the watch-
dog timer restarts a count (Note). On the other hand, at execution
of the WIT instruction, the watchdog timer does not stop.
The time from execution of writing to the watchdog timer control
register until an underflow of the watchdog timer register H is as
follows: (When bit 7 of the watchdog timer control register is “0”)
Middle / High-speed mode (f(X
IN
)=8 MHz).................. 32.768 ms
Low-speed mode (f(X
CIN
)=32 kHz) ..................................... 8.19 s
Note:
During the stop release wait time [X
IN
(or X
CIN
) : about 8200
clock cycles], the watchdog timer counts.
Accordingly, does not underflow the watchdog timer H.
Fig. 30 Structure of watchdog timer control register
Fig. 29 Watchdog timer block diagram
X
IN
Data bus
X
CIN
“1”
“0”
Internal system
clock selection bit
(Note)
“0”
“1”
1/16
Watchdog timer H
count source selection bit
Reset circuit
Undefined instruction
Reset
Watchdog timer H (6)
When writing to
watchdog timer control
register
set “3F
16
”
Internal reset
RESET
Watchdog timer L (8)
When writing to
watchdog timer
control register
set “FF
16
”
Note:
This bit is bit 7 of CPU mode register. It selects the mode (middle/high-speed or low-speed)
Reset release wait time (about 8200 X
IN
clock cycles)
Watchdog timer H bits (read only)
Not used (returns “1” when read)
Watchdog timer H count source selection bit
0 : Underflow from watchdog timer L
1 : f(X
IN
)/16 or f(X
CIN
)/16
Watchdog timer control register
(WDTCON : address 0037
16
)
7
0
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相關代理商/技術參數(shù) |
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|---|---|
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