參數(shù)資料
型號: 3256E
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable High Density PLD
中文描述: 在系統(tǒng)可編程高密度可編程邏輯器件
文件頁數(shù): 10/15頁
文件大?。?/td> 159K
代理商: 3256E
Specifications
ispLSI 3256E
10
Power Consumption
Figure 3 shows the relationship between power and
operating speed.
Power consumption in the ispLSI 3256E device depends
on two primary factors: the speed at which the device is
operating and the number of product terms used.
0127/3256E
ICC can be estimated for the ispLSI 3256E using the following equation:
ICC = 60 + (# of PTs * 0.48) + (# of nets * Max. freq * 0.0106) where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two
GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to
operating conditions and the program in the device, the actual ICC should be verified.
200
400
600
500
300
0
20
40
60
80
100
f
max (MHz)
I
C
Notes: Configuration of 16 16-bit Counters
Typical Current at 5V, 25
°
C
ispLSI 3256E
Figure 3. Typical Device Power Consumption vs fmax
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