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參數(shù)資料
| 型號(hào)： | 3256E |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大?。?/td> | 159K |
| 代理商： | 3256E |
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ispLSI
3256E
In-System Programmable High Density PLD
3256e_08
1
Features
HIGH-DENSITY PROGRAMMABLE LOGIC
— 256 I/O Pins
— 12000 PLD Gates
— 512 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
—
f
max
= 100 MHz Maximum Operating Frequency
—
t
pd
= 10 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
IN-SYSTEM PROGRAMMABLE
— 5V In-System Programmable (ISP) using Lattice
ISP or Boundary Scan Test (IEEE 1149.1) Protocol
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Five Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to Mini-
mize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
ispDesignEXPERT – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER
— PC and UNIX Platforms
Functional Block Diagram
C0
C1
C2
C3
ORP
ORP
Global Routing Pool
O
D0
D1
D2
D3
H3
H2
H1
H0
G3
G2
G1
G0
B0
B1
B2
B3
Boundary
Scan
OR
Array
D Q
D Q
D Q
D Q
Twin
GLB
OR
Array
D Q
D Q
D Q
D Q
A
O
A0
A1
A2
A3
E3
E2
E1
E0
F3
F2
F1
F0
0139A/3256E
ORP
ORP
ORP
ORP
ORP
ORP
O
O
O
O
O
O
Description
The ispLSI 3256E is a High Density Programmable Logic
Device containing 512 Registers, 256 Universal I/O pins,
five Dedicated Clock Input Pins, 16 Output Routing Pools
(ORP) and a Global Routing Pool (GRP) which allows
complete inter-connectivity between all of these ele-
ments. The ispLSI 3256E features 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 3256E offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 3256E device is the
Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3.
There are a total of 32 Twin GLBs in the ispLSI 3256E
device. Each Twin GLB has 24 inputs, a programmable
AND array and two OR/Exclusive-OR Arrays and eight
outputs which can be configured to be either combinato-
rial or registered. All Twin GLB inputs come from the
GRP.
Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
June 2002
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| 3266P-1-100A | 1/4 Square Trimming Potentiometer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3256TT | 功能描述:1-1/16'' BROAD BULL PIN WITH TET 制造商:klein tools, inc. 系列:- 零件狀態(tài):在售 工具類型:牛角插針 配套使用產(chǎn)品/相關(guān)產(chǎn)品:定位孔 重量:1.5 磅（680.4g） 標(biāo)準(zhǔn)包裝:3 |
| 3257 | 功能描述:塑料硬件 SW 2 SNUB BUSHING RoHS:否 制造商:3M Electronic Specialty 類型:Cylindrical Bumpers |
| 3257.0321 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HANDLE LEG OFFSET NAT 32MM |
| 3257.0323 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HANDLE LEG OFFSET BLK 32MM PK2 |
| 3257.0421 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HANDLE LEG OFFSET NAT 32MM PK2 |
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