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參數(shù)資料
| 型號： | 29LV800TE |
| 廠商： | Fujitsu Limited |
| 英文描述： | 8M (1M x 8/512 K x 16) BIT |
| 中文描述： | 8米（3米x五百一十二分之八畝× 16）位 |
| 文件頁數(shù)： | 23/58頁 |
| 文件大?。?/td> | 292K |
| 代理商： | 29LV800TE |
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MBM29LV800TE/BE
60/70/90
22
Write Operation Status
Hardware Sequence Flags
*1 : Performing successive read operations from any address will cause DQ
6
to toggle.
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to toggle.
Notes :
DQ
1
and DQ
0
are reserved pins for future use.
DQ
4
is Fujitsu internal use only.
DQ
7
Data Polling
The MBM29LV800TE/BE devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read devices
will produce a complement of data last written to DQ
7
. Upon completion of the Embedded Program Algorithm,
an attempt to read device will produce true data last written to DQ
7
. During the Embedded Erase Algorithm, an
attempt to read device will produce a “0” at the DQ
7
output. Upon completion of the Embedded Erase Algorithm
an attempt to read device will produce a “1” on DQ
7
. The flowchart for Data Polling (DQ
7
) is shown in “Data
Polling Algorithm” in “
I
FLOW CHART”.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected
sectors. Otherwise, the status may be invalid. Once the Embedded Algorithm operation is close to completion,
MBM29LV800TE/BE data pins (DQ
7
) may change asynchronously while the output enable (OE) is asserted low.
This means that devices are driving status information on DQ
7
at one instant of time and then that byte’s valid
data at the next instant of time. Depending on when the system samples the DQ
7
output, it may read the status
or valid data. Even if device has completed the Embedded Algorithm operation and DQ
7
has a valid data, data
outputs on DQ
6
to DQ
0
may be still invalid. The valid data on DQ
7
to DQ
0
will be read on the successive read
attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out.
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “
I
TIMING DIAGRAM” for the
Data Polling timing specifications and diagrams.
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase
Suspended
Mode
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
0
Toggle
Erase Suspend Read
(Non-Erase Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle*
1
0
0
1*
2
Exceeded
Time Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ
7
Toggle
1
0
N/A
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