參數(shù)資料
型號(hào)： 28F200BX
廠商： Intel Corp.
英文描述： 2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
中文描述： 2兆位（128K的× 16，256K × 8）啟動(dòng)塊閃存系列
文件頁(yè)數(shù)： 4/55頁(yè)
文件大?。?/td> 636K
代理商： 28F200BX
2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
4
SEE NEW DESIGN RECOMMENDATIONS
REVISION HISTORY
Number
Description
-001
Initial release of datasheet.
-002
Status changed from Product Preview to Preliminary
28F200CV/CE/BE references and information added throughout.
2.7 V CE/BE specs added throughout.
The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,
3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to
“Applying V
CC
Voltages.” These sections completely
changed to clarify V
CC
ramp requirements.
I
PPD
3.3 V Commercial spec changed from 10 to 5
μ
A.
Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component
values in table. (Component values also rounded off).
t
ELFL
, t
ELFH
, t
AVFL
changed from 7 to 5 ns for 3.3 V BV-60 commercial and 3.3 V
TBV-80 extended, 10 to 5 ns for 3.3 V BV-80 and BV-120 commercial.
t
WHAX
and t
EHAX
changed from 10 to 0 ns.
t
PHWL
changed from 1000 ns to 800 ns for 3.3 V BV-80, BV-120 commercial.
t
PHEL
changed from 1000 ns to 800 ns for 3.3 V BV-60, BV-80, and BV-120 commercial.
-003
Applying V
CC
voltages (Sections 5.1 and 6.1) rewritten for clarity.
Minor cosmetic changes/edits.
-004
Corrections: “This pin not available on 44-PSOP” inaccurate statement removed from pin
description for WP# pin; Spec “t
QWL
” corrected to “t
QVVL;
” intelligent identifier values
corrected; Intel386 EX block diagram updated because new 386 specs require less
glue logic.
Max program times for parameter and 96-KB main block added.
Specs t
ELFL
and t
ELFH
changed from 5 ns (max) to 0 ns (min).
Specs t
EHQZ
and t
HQZ
improved.
New specs t
PLPH
and t
PLQZ
added from Specification Update document (297612).
-005
Corrections: Figure 4, corrected pin designation 3 to “NC” from A
17
on PA28F200.
Corrected typographical errors in
Ordering Information
.
Added
New Design Recommendations
section to cover page.
Updated
Erase Suspend/Resume Flowchart
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
28F200BX-B 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F200BX-B - 2-MBIT (128K x 16. 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
28F200BX-T 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:28F200BX-T - 2-MBIT (128K x 16. 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
28F200BX-T/B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
28F200BX-TB 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8) BOOT BLOCK FLASH MEMORY FAMILY
28F200BX-TL/BL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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