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| 型號(hào)： | 28230-13 |
| 廠商： | CONEXANT SYSTEMS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM SEGMENTATION AND REASSEMBLY DEVICE, PQFP208 |
| 封裝： | PLASTIC, MQFP-208 |
| 文件頁(yè)數(shù)： | 190/237頁(yè) |
| 文件大?。?/td> | 3214K |
| 代理商： | 28230-13 |
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43
3.0 Functional Description
3.3 Local Processor Interface
Bt8230
ATM Segmentation and Reassembly Controller—SAR
N8230DS1F
are that the PBSEL[1,0] inputs may be driven by lower order address lines, and
there will be less than 17 address lines to buffer. Therefore, in most applications,
the data transceivers may utilize two by_16 parts, such as a 74ABT16245, and the
address buffer may utilize a single by_16 74ABT16244.
NOTE:
The i960CA/CF signals a failure of its internal self-test upon reset or
power-up by asserting its FAIL* output. This line is connected to the
PFAIL* pin of the Bt8230, and the status of this pin is reflected in the Host
Interrupt Status Register [HOST_ISTAT0; 0xC0].
3.3.4 i80960Jx Operating Mode
The major difference between the i80960Jx and the i80960CA processors is that
the Jx uses a multiplexed address/data bus structure while the CA/CF is non-mul-
tiplexed. However, in the Bt8230 system, the demultiplexing of addresses/data
takes place on the processor side of the address buffers and, therefore, does not
affect the Bt8230. Otherwise, the Jx has the same bus control signals as the
CA/CF with the exception of the WAIT* signal, which the Jx does not possess.
The insertion of wait states, if required, must be accomplished by an external
memory controller which, in any case, is required for a Jx implementation.
3.3.5 Stand-alone Operation
When the local processor is not used, the Bt8230 is said to be in Stand-alone
mode. Stand-alone interface pins and descriptions are given in Table 3-3.
Figure 3-16 shows the signal interface between the Bt8230 and the Bt8222 ATM
receiver/transmitter device with no local processor. The PCS*, PAS*, and PWNR
pins are now outputs providing chip select, address strobe, and write/read control
to the Bt8222. PDAEN* is now an input connected to the interrupt sources of the
Bt8222. PBLAST* is a second chip select which may be used to connect the
Bt8370 T1/E1 framer Line Interface Unit (LIU) since the Bt8222 does not con-
tain the LIU function. The PRDY* output is active and indicates the cycles in
which the data transaction occurs. The PWAIT* input is active and may be used to
prolong the cycle as shown in Figure 3-17. Physical interface devices other than
the Bt8222 may be connected by using PWAIT* to extend the read or write cycle
and by using external logic to translate the Bt8230 control signals.
Table 3-3. Stand-Alone Interface Pins (1 of 2)
Signal
Dir1
Description
PROCMODE
I
Processor interface mode select. A logic 1 enables stand-alone operation without a local processor.
PCS*
O
Chip select output for PHY device number 1. Synchronous to SYSCLK. See Figure 3-16.
PBLAST*
O
Chip select output for PHY device number 2. Synchronous to SYSCLK. See Figure 3-16.
PAS*
O
PHY address strobe. Synchronous to SYSCLK.
PWNR
O
PHY write/read select. A logic one on this output indicates a write cycle, a logic zero indicates a read
cycle. Synchronous to SYSCLK.
PRDY*
O
PHY interface ready signal. A logic low on this signal at rising edge of SYSCLK indicates that the
data cycle has been completed
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