參數(shù)資料
型號(hào): 25AA512
廠商: Microchip Technology Inc.
英文描述: 512 Kbit SPI Bus Serial EEPROM
中文描述: 512千位SPI總線串行EEPROM
文件頁(yè)數(shù): 14/32頁(yè)
文件大?。?/td> 485K
代理商: 25AA512
25AA512/25LC512
DS22021B-page 14
Preliminary
2007 Microchip Technology Inc.
2.8
PAGE ERASE
The
PAGE ERASE
instruction will erase all bits (FFh)
inside the given page. A Write Enable (
WREN
) instruc-
tion must be given prior to attempting a
PAGE ERASE
.
This is done by setting CS low and then clocking out
the proper instruction into the 25XX512. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The
PAGE ERASE
instruction is entered by driving CS
low, followed by the instruction code (Figure 2-8) and
two address bytes. Any address inside the page to be
erased is a valid address.
CS must then be driven high after the last bit of the
address or the
PAGE ERASE
will not execute. Once
the CS is driven high the self-timed
PAGE ERASE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the
PAGE ERASE
cycle
is complete.
If a
PAGE ERASE
instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
FIGURE 2-8:
PAGE ERASE SEQUENCE
SO
SI
SCK
CS
0
2
3
4
5
6
7
8
9 10 11
21 22 23
1
0
0
0
0
0
1
0
1
15 14 13 12
2
1
0
Instruction
16-bit Address
High-Impedance
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