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| 型號(hào)： | 25627A3 |
| 英文描述： | 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs |
| 中文描述： | 實(shí)現(xiàn)一個(gè)共同的AMD的MirrorBit布局？和英特爾StrataFlash？存儲(chǔ)設(shè)備 |
| 文件頁(yè)數(shù)： | 13/15頁(yè) |
| 文件大?。?/td> | 191K |
| 代理商： | 25627A3 |
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12
Implementing a Common Layout for AMD MirrorBit
TM
and Intel StrataFlash
TM
Memory Devices
Note:
Address must be on the bus long enough to be latched at both ends of WE#.
Figure 7.
AMD and Intel Address/Data Latching Techniques
Table 5.
AC Characteristics for Write Operations
Status Notification Schemes
Both AMD and Intel have simplified the work required
to design in flash by embedding the algorithms for
many common functions of the flash device. This al-
lows the device to act both as a memory device and a
peripheral unit to the CPU. As with any peripheral unit,
AMD and Intel flash devices also provide a method of
monitoring the status of these embedded operations.
The actual implementation however, does differ be-
tween the two manufacturers.
AMD provides a status register called the Operation
Status Bits that are multiplexed with the Data pins after
a Program or Erase operation begins. This register can
then be accessed by data polling the device using a
simple Read cycle. The host system is then free to per-
form other task and can poll the device periodically to
get latest status of the device.
Intel uses a similar status register, however the CPU
must issue a separate software command to poll the
register and a second command to clear the register.
AC Write Spec
AMD (ns)
32Mb-128Mb
Intel (ns)
32Mb–128Mb
Notes
Total Write Cycle
T
WC
90
(32,
64Mb)
100
(128,
256Mb)
T
WP
+
T
WPH
100
Minimum time between WP# assertions
Address Setup
T
AVWL
0
T
AVWH
55
Setup and hold times differ because of
different techniques used by AMD and Intel to
latch address data
Address Hold
T
WLAX
45
T
WHAX
0
Data Setup
T
DVWH
45
T
DVWH
50
Data must be setup earlier to accommodate
for Intel’s longer setup times
Data Hold
T
WHDX
0
T
WHDX
0
Write Pulse Width
T
WLWH
35
T
WPH
70
Write pulse width is directly related to data
setup time
Command Address
Program Address
Address
CE#
WE#
Data
Data
Data
Address
Address + Data
Address + Data
Address
CD
CD
AMD Address/Data Latching
Intel Address/Data Latching
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