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| 型號： | 25627A3 |
| 英文描述： | 2x4-Channel, Simultaneous-Sampling 12-Bit ADCs |
| 中文描述： | 實現(xiàn)一個共同的AMD的MirrorBit布局？和英特爾StrataFlash？存儲設(shè)備 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 191K |
| 代理商： | 25627A3 |
Implementing a Common Layout for AMD MirrorBit
TM
and Intel StrataFlash
TM
Memory Devices
11
Uniform vs. Boot Sectors
Boot sector devices differ from uniform sector devices
because they contain a group of smaller sectors either
at the top (top boot device) or bottom (bottom boot de-
vice) of the memory map. These smaller sectors are
usually used to store boot code or parametric data that
can be protected or updated separate from the remain-
ing sectors. The CFI algorithm in Figure 6 can be used
to detect whether a device has uniform or boot sectors.
AMD’s current LV320 is only offered with boot sectors
while Intel’s StrataFlash devices are only offered with
uniform sectors. Additional software would be required
to support both architectures in a dual layout.
Software for use with boot sector devices must be able
to handle these different sector sizes. Systems that are
read-only or use chip-erase to erase the entire device
need not worry about sector architecture. For more de-
tails on the differences between uniform or boot sec-
tors and the software requirements that need to be
considered, refer to AMD application note 22374 (Mi-
grating Between Boot and Uniform Sectored Flash De-
vice).
Design Considerations for AC Timing
Specs
Systems designers must account for differences in AC
Timing specifications for both read and write opera-
tions. One way to implement flexibility in the design is
to design the software to account for the worst-case
scenario using max timings of the slowest device, in
which case the tables below provide a clear compari-
son between vendors. Read timings as shown in Table
5, are much faster for AMD devices. If a designer wants
to take full advantage of faster access times for AMD
devices, the software driver can be written to fully opti-
mize timing characteristics by using CFI to query de-
vice timings to provide data for the appropriate timing
variables.
Table 4.
AC Characteristics for Read Operations
For write operations, the AC timings between AMD and
Intel devices differ far more because the two compa-
nies take a different approach to address and data
latching. AMD devices latch the address and data on
opposite ends of the write enable pulse (WE#). Intel
latches both address and data on the rising edge of the
write pulse. This results in some timing specifications
being defined differently between the two companies.
As a result, it is difficult to simply write a driver that que-
ries CFI and sets the appropriate variables to optimize
for program timings. For write operations, the design
should allow adequate time for the address and data to
be set up and latched on both the rising and falling
edges of the write enable pulse (see Figure 7).
JEDEC Spec
Description
AMD (ns)
Intel (ns)
32Mb, 64Mb
128Mb,
256Mb
32Mb
64Mb
128Mb
T
AVAV
Read Cycle Time (min)
90
100
110
120
150
T
AVQV
Address to Output Delay
90
100
110
120
150
T
ELQV
CE# to Output Delay
90
100
110
120
150
T
GLQV
OE# to Output Delay
30
50
T
EHQZ
CE# to Output High Z
16
55
T
GHQZ
OE# to Output High Z
16
15
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