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參數(shù)資料
| 型號： | 24WC32 |
| 元件分類： | EEPROM |
| 英文描述： | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| 中文描述： | 64K的8K的× 8電池電壓的CMOS E2PROM的 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 74K |
| 代理商： | 24WC32 |
Preliminary
CAT24WC32/64
4
Doc. No. 25053-00 2/98 S-1
FUNCTIONAL DESCRIPTION
The CAT24WC32/64 supports the I
2
C Bus data trans-
mission protocol. This Inter-Integrated Circuit Bus proto-
col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC32/64
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
PIN DESCRIPTIONS
SCL:
Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These pins are hardwired or left unconnected (for hard-
ware compatibility with CAT24WC16). When hardwired,
up to eight CAT24WC32/64s may be addressed on a
single bus system (refer to Device Addressing ). When
the pins are left unconnected, the default values are
zeros.
WP:
Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC32/64 when this pin
is tied to Vcc, the entire memory is write protected.
When left floating, memory is unprotected.
5020 FHD F05
Figure 3. Start/Stop Timing
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
START BIT
SDA
STOP BIT
SCL
5020 FHD F04
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
5020 FHD F03
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
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