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參數(shù)資料
| 型號： | 24WC128 |
| 元件分類： | EEPROM |
| 英文描述： | 64K 8K x 8 Battery-Voltage CMOS E2PROM |
| 中文描述： | 64K的8K的× 8電池電壓的CMOS E2PROM的 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 43K |
| 代理商： | 24WC128 |
Preliminary
CAT24WC128
7
Doc. No. 25060-00 6/99 S-1
READ operation. The Master device first performs a
‘
dummy
’
write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC128 acknowledges, the
Master device sends the START condition and the slave
address again, this time with the R/
W
bit set to one. The
CAT24WC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC128 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
Figure 8. Immediate Address Read Timing
24WC128 F10
SCL
SDA
8TH BIT
STOP
NO ACK
DATA OUT
8
9
SLAVE
ADDRESS
S
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
N
O
A
C
K
DATA
S
T
O
P
P
data. The CAT24WC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to re-
spond with an acknowledge, thus sending the STOP
condition.
The data being transmitted from CAT24WC128 is out-
putted sequentially with data from address N followed
by data from address N+1. The READ operation ad-
dress counter increments all of the CAT24WC128 ad-
dress bits so that the entire memory array can be read
during one operation. If more than E (where E=16383)
bytes are read out, the counter will
‘
wrap around
’
and
continue to clock out data bytes.
Figure 9. Selective Read Timing
24WC128 F11
*
=Don't Care Bit
A15
–
A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7
–
A0
BYTE ADDRESS
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
A
R
T
DATA
P
S
T
O
P
*
*
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